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| author | Furquan Shaikh <furquan@google.com> | 2020-06-30 14:08:27 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-07-01 19:32:01 +0000 |
| commit | 489ffefef6fdf40d1f877f6b3b5c10f45e52c3eb (patch) | |
| tree | d3102a11043429e4aa976623515a27bd08791d6e /src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c | |
| parent | ffbf5d9818e1ce348f88c2a376cb627b48cdc1bb (diff) | |
| download | coreboot-489ffefef6fdf40d1f877f6b3b5c10f45e52c3eb.tar.gz coreboot-489ffefef6fdf40d1f877f6b3b5c10f45e52c3eb.tar.bz2 coreboot-489ffefef6fdf40d1f877f6b3b5c10f45e52c3eb.zip | |
mb/google/zork: Move EC wake to happen in ramstage
Currently, EC wake signal (GPIO_24) is configured early on in
romstage. However, there is no need for that since EC wake is not
really required to be configured until ramstage. This change moves
GPIO_24 configuration to happen in ramstage.
BUG=b:159832123
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6949dcd7c866df2fa028c7b2e7f347cec988e309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42952
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 75a7096cc2fb..ea858195a57c 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -12,8 +12,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { /* PEN_POWER_EN - reset */ PAD_GPO(GPIO_5, LOW), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -45,8 +43,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = { PAD_GPO(GPIO_5, LOW), /* EN_PWR_TOUCHPAD_PS2 - reset */ PAD_GPO(GPIO_6, LOW), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -109,6 +105,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_UP), /* */ |