diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-07-13 16:07:12 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-15 08:34:29 +0000 |
| commit | 0c0bcd4072746582d8837dd7eca2f1731ce35561 (patch) | |
| tree | ceffd06a146e1b6e1688cfc6d6e7d7bef96b4130 /src/mainboard/google/zork/variants/baseboard/include | |
| parent | 7c1fe4bd122602272a3f2c7d7c2fbc3124cf2f8d (diff) | |
| download | coreboot-0c0bcd4072746582d8837dd7eca2f1731ce35561.tar.gz coreboot-0c0bcd4072746582d8837dd7eca2f1731ce35561.tar.bz2 coreboot-0c0bcd4072746582d8837dd7eca2f1731ce35561.zip | |
PCI IDs: Add PCI ID for JSL DPTF/DTT PCI device
This PCI ID is required in order for JSL devices to perform SSDT
generation for DPTF.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/include')
0 files changed, 0 insertions, 0 deletions