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| author | Aaron Durbin <adurbin@chromium.org> | 2020-07-02 11:08:21 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-07-03 15:36:30 +0000 |
| commit | 76fcf82901af76cd70bdac7fbfddf58f41770d0a (patch) | |
| tree | 4dd1fbbeb0333631b2722bb45ed707824e273396 /src/mainboard/google/zork/variants/baseboard/include | |
| parent | d3758540a951510ede21ebb76cbc196ae8ed0e68 (diff) | |
| download | coreboot-76fcf82901af76cd70bdac7fbfddf58f41770d0a.tar.gz coreboot-76fcf82901af76cd70bdac7fbfddf58f41770d0a.tar.bz2 coreboot-76fcf82901af76cd70bdac7fbfddf58f41770d0a.zip | |
mb/google/zork: adjust eSPI virtual irq settings
The eSPI polarity macros were reversed. Those are fixed so adjust
the corresponding values related to the correct expectations of
the IRQ path: eSPI virtual wire IRQs are active level high. The EC
sends active level high virtual wire IRQs. The default interrupt
encodings in ACPI for P2/S devices are active edge high. Therefore,
there is no need to override anything.
BUG=b:157984427
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia28d82cd9e432df98839f68bac4eae4447455e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/include')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h index 8ef0645afd3b..ff42989286e0 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h @@ -59,8 +59,6 @@ #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ -#define SIO_EC_PS2K_IRQ IRQ (Level, ActiveHigh, Exclusive) {1} -#define SIO_EC_PS2M_IRQ IRQ (Level, ActiveHigh, Exclusive) {12} /* * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in |