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| author | Aaron Durbin <adurbin@chromium.org> | 2020-07-29 13:54:22 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-07-30 20:05:55 +0000 |
| commit | 80e2dd88542581fe637b3ee7825bfe4c65811bba (patch) | |
| tree | bf091e007ec8db33b03f2da5b7245aad703959f3 /src/mainboard/google/zork/variants/baseboard/include | |
| parent | 821b1e2f28b875f353b30bcd6b286d3eeae85c7b (diff) | |
| download | coreboot-80e2dd88542581fe637b3ee7825bfe4c65811bba.tar.gz coreboot-80e2dd88542581fe637b3ee7825bfe4c65811bba.tar.bz2 coreboot-80e2dd88542581fe637b3ee7825bfe4c65811bba.zip | |
mb/google/zork: remove indirection for dxio lane configuration
There was a mix of open coding DXIO logical lane numbers and clkreq
pins. And there are separate macros depending on the baseboard
as well as processor type. Remove the indirection and supply the values
directly in the descriptors.
BUG=b:162423378
Change-Id: I779cb0a514e3b668265e6039d6e7e7bd0f3d49ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/include')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h index 84433e062255..389f0e832a58 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h @@ -7,31 +7,10 @@ #include <soc/gpio.h> #include <platform_descriptors.h> -#define WLAN_CLKREQ CLK_REQ0 -#define SD_CLKREQ CLK_REQ1 - -#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ) -#define NVME_START_LANE 4 -#define NVME_END_LANE 5 -#define WLAN_START_LANE 0 -#define WLAN_END_LANE 0 -#define SD_START_LANE 1 -#define SD_END_LANE 1 -#else -#define NVME_START_LANE 0 -#define NVME_END_LANE 1 -#define WLAN_START_LANE 4 -#define WLAN_END_LANE 4 -#define SD_START_LANE 5 -#define SD_END_LANE 5 -#endif - #if CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE) #define EC_IN_RW_OD GPIO_130 -#define NVME_CLKREQ CLK_REQ4 #else #define EC_IN_RW_OD GPIO_11 -#define NVME_CLKREQ CLK_REQ2 #endif /* SPI Write protect */ |