mb/google/zork: Add Picasso based Zork mainboard and variants

This is a copy of the mb/google/zork directory from the chromiumos
coreboot-zork branch. This was from commit 29308ac8606.

See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork

Changes:
* Minor changes to make the board build.
* Add bootblock.c.
* Modify romstage.c
* Removed the FSP_X configs from zork/Kconfig since they should be
  set in picasso/Kconfig. picasso/Kconfig doesn't currently define the
  binaries since they haven't been published. To get a working build
  a custom config that sets FSP_X_FILE is required.

BUG=b:157140753
TEST=Build trembyle and boot to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 690 insertions, 0 deletions

diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl
new file mode 100644
index 000000000000..ae5663e7c75c
--- /dev/null
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+Scope (EC0.CREC) {
+	#include <ec/google/chromeec/acpi/codec.asl>
+}
+
+/* machine driver */
+Device (I2SM)
+{
+	Name (_HID, "AMDI5682")
+	Name (_UID, 1)
+	Name (_DDN, "I2S machine Driver")
+
+	Name (_CRS, ResourceTemplate ()
+	{
+#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ)
+		/* DMIC select GPIO */
+		GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
+			IoRestrictionNone, "\\_SB.GPIO", 0x00,
+			ResourceConsumer,,) { 6 }
+#else
+		/* DMIC select GPIO */
+		GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,
+			IoRestrictionNone, "\\_SB.GPIO", 0x00,
+			ResourceConsumer,,) { 13 }
+#endif
+	})
+	/* Device-Specific Data */
+	Name (_DSD, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package ()
+			{
+				"dmic-gpio", Package () { ^I2SM, 0, 0, 0 }
+			}
+		}
+
+	})
+	Method (_STA)
+	{
+		Return (0xF)
+	}
+}
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/mainboard.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/mainboard.asl
new file mode 100644
index 000000000000..b3d39969f1a9
--- /dev/null
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/mainboard.asl
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/* Memory related values */
+Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0)	/* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+/* Some global data */
+Name(OSVR, 3)	/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones)	/* Assume nothing */
+Name(PMOD, One)	/* Assume APIC */
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl
new file mode 100644
index 000000000000..21c31a3b011f
--- /dev/null
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+
+Device (AAHB)
+{
+	Name (_HID, "AAHB0000")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000)
+	})
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (GPIO)
+{
+	Name (_HID, GPIO_DEVICE_NAME)
+	Name (_CID, GPIO_DEVICE_NAME)
+	Name (_UID, 0)
+	Name (_DDN, GPIO_DEVICE_DESC)
+
+	Method(_CRS ,0) {
+		local0=ResourceTemplate(){
+			Interrupt (
+				ResourceConsumer,
+				Level,
+				ActiveLow,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
+		}
+		CreateDWordField(local0, IRQR._INT, IRQN)
+		If(PMOD) {
+			IRQN=IGPI
+		} Else {
+			IRQN=PGPI
+		}
+		If (IRQN == 0x1f) {
+			Return(ResourceTemplate(){
+				Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
+			})
+		} Else {
+			Return(local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (MMC0)
+{
+	Name (_HID, "AMDI0040")
+	Name (_UID, 0x0)
+	Method(_CRS ,0) {
+		local0=ResourceTemplate(){
+			Interrupt (
+				ResourceConsumer,
+				Level,
+				ActiveLow,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000)
+		}
+		CreateDWordField(local0, IRQR._INT, IRQN)
+		If(PMOD) {
+			IRQN=IMMC
+		} Else {
+			IRQN=PMMC
+		}
+		If (IRQN == 0x1f) {
+			Return(ResourceTemplate(){
+				Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000)
+			})
+		} Else {
+			Return(local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (FUR0)
+{
+	Name (_HID, "AMD0020")
+	Name (_UID, 0x0)
+	Method(_CRS ,0) {
+		local0=ResourceTemplate(){
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+			Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000)
+		}
+		CreateDWordField(local0, IRQR._INT, IRQN)
+		If(PMOD) {
+			IRQN=IUA0
+		} Else {
+			IRQN=PUA0
+		}
+		If (IRQN == 0x1f) {
+			Return(ResourceTemplate(){
+				Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+				Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000)
+			})
+		} Else {
+			Return(local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (FUR1) {
+	Name (_HID, "AMD0020")
+	Name (_UID, 0x1)
+	Method(_CRS ,0) {
+		local0=ResourceTemplate(){
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+			Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000)
+		}
+		CreateDWordField(local0, IRQR._INT, IRQN)
+		If(PMOD) {
+			IRQN=IUA1
+		} Else {
+			IRQN=PUA1
+		}
+		If (IRQN == 0x1f) {
+			Return(ResourceTemplate(){
+				Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+				Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000)
+			})
+		} Else {
+			Return(local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (I2C2) {
+	Name (_HID, "AMD0010")
+	Name (_UID, 0x2)
+	Method(_CRS ,0) {
+		local0=ResourceTemplate(){
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
+		}
+		CreateDWordField(local0, IRQR._INT, IRQN)
+		If(PMOD) {
+			IRQN=II22
+		} Else {
+			IRQN=PI22
+		}
+		If (IRQN == 0x1f) {
+			Return(ResourceTemplate(){
+				Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
+			})
+		} Else {
+			Return(local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (I2C3)
+{
+	Name (_HID, "AMD0010")
+	Name (_UID, 0x3)
+	Method(_CRS ,0) {
+		local0=ResourceTemplate(){
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
+		}
+		CreateDWordField(local0, IRQR._INT, IRQN)
+		If(PMOD) {
+			IRQN=II23
+		} Else {
+			IRQN=PI23
+		}
+		If (IRQN == 0x1f) {
+			Return(ResourceTemplate(){
+				Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
+			})
+		} Else {
+			Return(local0)
+		}
+	}
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (MISC)
+{
+	Name (_HID, "AMD0040")
+	Name (_UID, 0x3)
+	Name (_CRS, ResourceTemplate() {
+		Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl
new file mode 100644
index 000000000000..c8fb05fe1f81
--- /dev/null
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+*		-none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method.  This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver.  This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(_PTS, 1) {
+	/* DBGO("\\_PTS\n") */
+	/* DBGO("From S0 to S") */
+	/* DBGO(Arg0) */
+	/* DBGO("\n") */
+
+	/* Clear wake status structure. */
+	Store(0, PEWD)
+	Store(0, Index(WKST,0))
+	Store(0, Index(WKST,1))
+	Store(7, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+*	\_BFS OEM Back From Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		-none-
+*/
+Method(\_BFS, 1) {
+	/* DBGO("\\_BFS\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+}
+
+/*
+*  \_WAK System Wake method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		Return package of 2 DWords
+*		Dword 1 - Status
+*			0x00000000	wake succeeded
+*			0x00000001	Wake was signaled but failed due to lack of power
+*			0x00000002	Wake was signaled but failed due to thermal condition
+*		Dword 2 - Power Supply state
+*			if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+	/* DBGO("\\_WAK\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+
+	Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl
new file mode 100644
index 000000000000..8f5aa6ab5ebc
--- /dev/null
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <variant/thermal.h>
+
+/* Thermal Zone */
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		/* Thermal constants for passive cooling */
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		/* Thermal zone polling frequency: 10 seconds */
+		Name (_TZP, 100)
+
+		/* Thermal sampling period for passive cooling: 2 seconds */
+		Name (_TSP, 20)
+
+		/* Convert from Degrees C to 1/10 Kelvin for ACPI */
+		Method (CTOK, 1) {
+			/* 10th of Degrees C */
+			Multiply (Arg0, 10, Local0)
+
+			/* Convert to Kelvin */
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		/* Threshold for OS to shutdown */
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		/* Threshold for passive cooling */
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		/* Processors used for passive cooling */
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			/* Get temperature from EC in deci-kelvin */
+			Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0)
+
+			/* Critical temperature in deci-kelvin */
+			Store (CTOK (\TCRT), Local1)
+
+			If (LGreaterEqual (Local0, Local1)) {
+				Store ("CRITICAL TEMPERATURE", Debug)
+				Store (Local0, Debug)
+
+				/* Wait 1 second for EC to re-poll */
+				Sleep (1000)
+
+				/* Re-read temperature from EC */
+				Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0)
+
+				Store ("RE-READ TEMPERATURE", Debug)
+				Store (Local0, Debug)
+			}
+
+			Return (Local0)
+		}
+
+	}
+}
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 000000000000..8ef0645afd3b
--- /dev/null
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <variant/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/*
+ * EC can wake from S3 with lid or power button or key press or
+ * mode change event
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/* Enable LID switch */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN EC_WAKE_GPI
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K	/* Enable PS/2 Keyboard */
+#define SIO_EC_PS2K_IRQ		IRQ (Level, ActiveHigh, Exclusive) {1}
+#define SIO_EC_PS2M_IRQ		IRQ (Level, ActiveHigh, Exclusive) {12}
+
+/*
+ * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in
+ * variant/gpio.h
+ */
+#define EC_ENABLE_SYNC_IRQ_GPIO
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+/* Enable Tablet switch */
+#define EC_ENABLE_TBMC_DEVICE
+
+#endif
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 000000000000..4801a5ec7ba8
--- /dev/null
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#ifndef __ACPI__
+#include <soc/gpio.h>
+#include <platform_descriptors.h>
+
+#define H1_PCH_INT		GPIO_3
+#define PEN_DETECT_ODL		GPIO_4
+#define PEN_POWER_EN		GPIO_5
+#define TOUCHPAD_INT_ODL	GPIO_9
+#define EC_FCH_WAKE_L		GPIO_24
+#define WIFI_PCIE_RESET_L	GPIO_26
+#define PCIE_RST1_L		GPIO_27
+#define EN_PWR_WIFI		GPIO_29
+#define NVME_AUX_RESET_L	GPIO_40
+#define WIFI_AUX_RESET_L	GPIO_42
+#define EN_PWR_CAMERA		GPIO_76
+#define EN_PWR_TOUCHPAD_PS2	GPIO_67
+#define PCIE_0_WIFI_CLKREQ_ODL	GPIO_92
+#define PCIE_1_SD_CLKREQ_ODL	GPIO_115
+#define BIOS_FLASH_WP_ODL	GPIO_137
+#define SD_AUX_RESET_L		GPIO_142
+#define WLAN_CLKREQ		CLK_REQ0
+#define SD_CLKREQ		CLK_REQ1
+
+#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ)
+#define NVME_START_LANE 4
+#define NVME_END_LANE 5
+#define WLAN_START_LANE 0
+#define WLAN_END_LANE 0
+#define SD_START_LANE 1
+#define SD_END_LANE 1
+#else
+#define NVME_START_LANE 0
+#define NVME_END_LANE 1
+#define WLAN_START_LANE 4
+#define WLAN_END_LANE 4
+#define SD_START_LANE 5
+#define SD_END_LANE 5
+#endif
+
+#if CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE)
+#define FPMCU_INT_L		GPIO_6
+#define FPMCU_RST_ODL		GPIO_11
+#define EC_IN_RW_OD		GPIO_130
+#define PCIE_4_NVME_CLKREQ_ODL	GPIO_132
+#define NVME_CLKREQ		CLK_REQ4
+#else
+#define EC_IN_RW_OD		GPIO_11
+#define PCIE_2_NVME_CLKREQ_ODL	GPIO_116
+#define NVME_CLKREQ		CLK_REQ2
+#endif
+
+/* SPI Write protect */
+#define CROS_WP_GPIO		BIOS_FLASH_WP_ODL
+#define GPIO_EC_IN_RW		EC_IN_RW_OD
+
+/* PCIe reset pins */
+#define PCIE_0_RST		WIFI_AUX_RESET_L
+#define PCIE_1_RST		SD_AUX_RESET_L
+#define PCIE_2_RST		0
+#define PCIE_3_RST		0
+#define PCIE_4_RST		NVME_AUX_RESET_L
+
+#endif /* _ACPI__ */
+
+/* These define the GPE, not the GPIO. */
+#define EC_SCI_GPI		3	/* eSPI system event -> GPE 3 */
+#define EC_WAKE_GPI		15	/* AGPIO 24 -> GPE 15 */
+
+/* EC sync irq */
+#define EC_SYNC_IRQ		31
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h
new file mode 100644
index 000000000000..b3c951bbaf93
--- /dev/null
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+/*
+ * Picasso Thermal Requirements
+ * TDP (W) 15
+ * T die,max (°C) 105
+ * T ctl,max 105
+ * T die,lmt (default) 100
+ * T ctl,lmt (default) 100
+ */
+
+/* Control TDP Settings */
+#define CTL_TDP_SENSOR_ID		2	/* EC TIN2 */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE		104
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE		95
+
+#endif
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 000000000000..c682eca1a452
--- /dev/null
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <stddef.h>
+#include <boardid.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/platform_descriptors.h>
+#include "chip.h"
+
+const struct sci_source *get_gpe_table(size_t *num);
+const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
+const struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size);
+const struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size);
+/*
+ * This function provides base GPIO configuration table. It is typically provided by
+ * baseboard using a weak implementation. If GPIO configuration for a variant differs
+ * significantly from the baseboard, then the variant can also provide a strong implementation
+ * of this function.
+ */
+const struct soc_amd_gpio *variant_base_gpio_table(size_t *size);
+/*
+ * This function allows variant to override any GPIOs that are different than the base GPIO
+ * configuration provided by variant_base_gpio_table().
+ */
+const struct soc_amd_gpio *variant_override_gpio_table(size_t *size);
+void variant_romstage_entry(void);
+/* Modify devictree settings during ramstage. */
+void variant_devtree_update(void);
+
+/* Per variant FSP-S initialization, default implementation in baseboard and
+ * overrideable by the variant. */
+void variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs,
+				      size_t *pcie_num,
+				      const picasso_fsp_ddi_descriptor **ddi_descs,
+				      size_t *ddi_num);
+
+/* Provide the descriptors for the associated baseboard for the variant. These functions
+ * can be used for obtaining the baseboard's descriptors if the variant followed the
+ * baseboard. */
+const picasso_fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num);
+const picasso_fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num);
+
+/* Retrieve attributes from FW_CONFIG in CBI. */
+/* Return 1 if FW_CONFIG expected to be valid, else 0. */
+int variant_fw_config_valid(void);
+/* Return 0 if non-existent, 1 if present. */
+int variant_has_emmc(void);
+/* Return 0 if non-existent, 1 if present. */
+int variant_has_nvme(void);
+
+/* Determine if booting in factory by using CROS_SKU_UNPROVISIONED. */
+int boot_is_factory_unprovisioned(void);
+
+#endif /* __BASEBOARD_VARIANTS_H__ */