mb/google/zork: Move variant_early_gpio_table to gpio_baseboard_common.c

This change moves the GPIOs that need to be configured for early
access in coreboot to early_gpio_table[] in
gpio_baseboard_common.c. These GPIOs include:
* Pads to talk to EC
* Pads to talk to TPM
* Pads to talk to serial console

These should be configured in the first stage that runs coreboot
i.e. in case of VBOOT_STARTS_BEFORE_BOOTBLOCK, it should be done as
part of verstage (which starts on PSP), else it should be done as part
of bootblock (which is the first stage that runs on x86).

This change drops GPIO_137 from early_gpio_table since that is not
really required in early stages.

BUG=b:154351731
TEST=Verified that trembyle still boots.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifbdbb02cbfc65ddb68f0ae75cf4b1f2ea1656b91
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252709
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 34 insertions, 86 deletions

diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc
index 4bcaf68aedfe..7e4ccae4f3f2 100644
--- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc
@@ -1,18 +1,22 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
+bootblock-y += gpio_baseboard_common.c
 bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c
 bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c
 
+verstage-y += gpio_baseboard_common.c
 ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
 verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c
 verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c
 endif
 verstage-y += tpm_tis.c
 
+romstage-y += gpio_baseboard_common.c
 romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c
 romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c
 romstage-y += tpm_tis.c
 
+ramstage-y += gpio_baseboard_common.c
 ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c
 ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += fsps_baseboard_trembyle.c
 ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
new file mode 100644
index 000000000000..e903700d0f63
--- /dev/null
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+#include <stdlib.h>
+#include <boardid.h>
+#include <variant/gpio.h>
+
+static const struct soc_amd_gpio early_gpio_table[] = {
+	/* H1_FCH_INT_ODL */
+	PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS),
+	/* I2C3_SCL - H1 */
+	PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),
+	/* I2C3_SDA - H1 */
+	PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
+	/* FCH_ESPI_EC_CS_L */
+	PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
+	/* ESPI_ALERT_L (may be unused) */
+	PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP),
+	/* UART0_RXD - DEBUG */
+	PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
+	/* UART0_TXD - DEBUG */
+	PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
+};
+
+const __weak struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
+{
+	*size = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index b5b284784125..46c232129a20 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -7,37 +7,9 @@
 #include <boardid.h>
 #include <variant/gpio.h>
 
-static const struct soc_amd_gpio gpio_set_stage_reset[] = {
-	/* H1_FCH_INT_ODL */
-	PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS),
-	/* I2C3_SCL - H1 */
-	PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),
-	/* I2C3_SDA - H1 */
-	PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
-
-	/* FCH_ESPI_EC_CS_L */
-	PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
-
-	/* ESPI_ALERT_L (may be unused) */
-	PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP),
-
-	/* UART0_RXD - DEBUG */
-	PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
-	/* BIOS_FLASH_WP_ODL */
-	PAD_GPI(GPIO_137, PULL_NONE),
-	/* UART0_TXD - DEBUG */
-	PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
-};
-
 static const struct soc_amd_gpio gpio_set_stage_rom[] = {
-	/* H1_FCH_INT_ODL */
-	PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS),
 	/* PEN_POWER_EN - reset */
 	PAD_GPO(GPIO_5, LOW),
-	/* I2C3_SCL - H1 */
-	PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),
-	/* I2C3_SDA - H1 */
-	PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
 	/* EC_FCH_WAKE_L */
 	PAD_GPI(GPIO_24, PULL_UP),
 	PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
@@ -46,8 +18,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom[] = {
 	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
 	/* PCIE_RST1_L - Variable timings (May remove) */
 	PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
-	/* FCH_ESPI_EC_CS_L */
-	PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
 	/* NVME_AUX_RESET_L */
 	PAD_GPO(GPIO_40, HIGH),
 	/* WIFI_AUX_RESET_L */
@@ -60,18 +30,12 @@ static const struct soc_amd_gpio gpio_set_stage_rom[] = {
 	PAD_GPO(GPIO_76, LOW),
 	/* CLK_REQ0_L - WIFI */
 	PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
-	/* ESPI_ALERT_L (may be unused) */
-	PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP),
 	/* CLK_REQ1_L - SD Card */
 	PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
 	/* CLK_REQ2_L - NVMe */
 	PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP),
-	/* UART0_RXD - DEBUG */
-	PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
 	/* BIOS_FLASH_WP_ODL */
 	PAD_GPI(GPIO_137, PULL_NONE),
-	/* UART0_TXD - DEBUG */
-	PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
 	/* USI_RESET - reset */
 	PAD_GPO(GPIO_140, HIGH),
 	/* USB_HUB_RST_L - reset*/
@@ -198,13 +162,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 };
 
 const __weak
-struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
-{
-	*size = ARRAY_SIZE(gpio_set_stage_reset);
-	return gpio_set_stage_reset;
-}
-
-const __weak
 struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
 {
 	*size = ARRAY_SIZE(gpio_set_stage_rom);
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index 6101330a7961..c3e1e42f3583 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -7,37 +7,9 @@
 #include <boardid.h>
 #include <variant/gpio.h>
 
-static const struct soc_amd_gpio gpio_set_stage_reset[] = {
-	/* H1_FCH_INT_ODL */
-	PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS),
-	/* I2C3_SCL - H1 */
-	PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),
-	/* I2C3_SDA - H1 */
-	PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
-
-	/* FCH_ESPI_EC_CS_L */
-	PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
-
-	/* ESPI_ALERT_L (may be unused) */
-	PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP),
-
-	/* UART0_RXD - DEBUG */
-	PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
-	/* BIOS_FLASH_WP_ODL */
-	PAD_GPI(GPIO_137, PULL_NONE),
-	/* UART0_TXD - DEBUG */
-	PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
-};
-
 static const struct soc_amd_gpio gpio_set_stage_rom[] = {
-	/* H1_FCH_INT_ODL */
-	PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS),
 	/* PEN_POWER_EN - reset */
 	PAD_GPO(GPIO_5, LOW),
-	/* I2C3_SCL - H1 */
-	PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),
-	/* I2C3_SDA - H1 */
-	PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
 	/* EC_FCH_WAKE_L */
 	PAD_GPI(GPIO_24, PULL_UP),
 	PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
@@ -46,8 +18,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom[] = {
 	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
 	/* PCIE_RST1_L - Variable timings (May remove) */
 	PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
-	/* FCH_ESPI_EC_CS_L */
-	PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
 	/* NVME_AUX_RESET_L */
 	PAD_GPO(GPIO_40, HIGH),
 	/* WIFI_AUX_RESET_L */
@@ -62,8 +32,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom[] = {
 	PAD_GPI(GPIO_84, PULL_NONE),
 	/* CLK_REQ0_L - WIFI */
 	PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
-	/* ESPI_ALERT_L (may be unused) */
-	PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP),
 	/* CLK_REQ1_L - SD Card */
 	PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
 	/*  RAM_ID_3  */
@@ -76,12 +44,8 @@ static const struct soc_amd_gpio gpio_set_stage_rom[] = {
 	PAD_GPI(GPIO_131, PULL_NONE),
 	/* CLK_REQ4_L - SSD */
 	PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP),
-	/* UART0_RXD - DEBUG */
-	PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
 	/* BIOS_FLASH_WP_ODL */
 	PAD_GPI(GPIO_137, PULL_NONE),
-	/* UART0_TXD - DEBUG */
-	PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
 	/* USI_RESET - reset */
 	PAD_GPO(GPIO_140, HIGH),
 	/* SD_AUX_RESET_L */
@@ -207,13 +171,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 };
 
 const __weak
-struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
-{
-	*size = ARRAY_SIZE(gpio_set_stage_reset);
-	return gpio_set_stage_reset;
-}
-
-const __weak
 struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
 {
 	*size = ARRAY_SIZE(gpio_set_stage_rom);