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| author | Furquan Shaikh <furquan@google.com> | 2020-08-28 12:16:23 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-08-31 17:49:25 +0000 |
| commit | 000003ea1e2e741def558806bf24e8507792bf56 (patch) | |
| tree | 9d190bbba3f01e92e4fbec3862622a2dbd873ec6 /src/mainboard/google/zork/variants/berknip | |
| parent | e8286633924ba889db691bd71ed059d847ecff6c (diff) | |
| download | coreboot-000003ea1e2e741def558806bf24e8507792bf56.tar.gz coreboot-000003ea1e2e741def558806bf24e8507792bf56.tar.bz2 coreboot-000003ea1e2e741def558806bf24e8507792bf56.zip | |
mb/google/zork: Fix active polarity of touchscreen reset GPIO in overridetree
v3.6+ of reference schematics have moved to using active low polarity
for touchscreen GPIO. This change sets the default polarity in
override tree accordingly to active low. To support boards from older
builds, variant_touchscreen_update() already updates the polarity to
active high.
BUG=b:161937506
Change-Id: I370bdb27ea5d0601612d13b515113a6048018964
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/berknip')
| -rw-r--r-- | src/mainboard/google/zork/variants/berknip/overridetree.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index bdda03426769..9797b469fa96 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -68,7 +68,7 @@ chip soc/amd/picasso register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "enable_delay_ms" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" # 32ms: Rise time of the reset line # 20ms: Firmware ready time register "reset_delay_ms" = "32 + 20" @@ -83,7 +83,7 @@ chip soc/amd/picasso register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "enable_delay_ms" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" register "has_power_resource" = "1" device i2c 10 on end @@ -95,7 +95,7 @@ chip soc/amd/picasso register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "generic.enable_delay_ms" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "50" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" |