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| author | Furquan Shaikh <furquan@google.com> | 2020-06-18 01:44:21 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-06-25 08:08:15 +0000 |
| commit | 462f3ed111e049cc95e2ee2ce4f4e88a415cc912 (patch) | |
| tree | b1381f2a35ee8cbea14c199ea4f3f71fb92e9a51 /src/mainboard/google/zork/variants/dalboz | |
| parent | da459c46bdbb3bb50ef0680d069bf5e47a7d5fad (diff) | |
| download | coreboot-462f3ed111e049cc95e2ee2ce4f4e88a415cc912.tar.gz coreboot-462f3ed111e049cc95e2ee2ce4f4e88a415cc912.tar.bz2 coreboot-462f3ed111e049cc95e2ee2ce4f4e88a415cc912.zip | |
mb/google/zork: Update ramstage GPIOs for v3 schematics for dalboz reference
This change updates the baseboard GPIO table in ramstage to match
v3 version of dalboz reference schematics. All variants using this
reference are accordingly updated to configure the GPIOs that changed
as part of v3 schematics.
BUG=b:157165628, b:157744136, b:157743835
TEST=Compiles
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If9d0e35801f9f9b15eddeb4ec7068fed6d401307
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251394
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Auto-Submit: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/dalboz')
| -rw-r--r-- | src/mainboard/google/zork/variants/dalboz/gpio.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c index 3e705a6b34cf..a4813e90fba9 100644 --- a/src/mainboard/google/zork/variants/dalboz/gpio.c +++ b/src/mainboard/google/zork/variants/dalboz/gpio.c @@ -9,12 +9,23 @@ /* This table is used by dalboz variant with board version < 2. */ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { + /* DMIC_SEL */ + PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC /* USB_OC2_L - USB A0 & A1 */ PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + /* EN_PWR_TOUCHPAD_PS2 */ + PAD_GPO(GPIO_67, HIGH), /* Unused */ PAD_GPI(GPIO_143, PULL_DOWN), }; +static const struct soc_amd_gpio bid_2_gpio_set_stage_ram[] = { + /* DMIC_SEL */ + PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC + /* EN_PWR_TOUCHPAD_PS2 */ + PAD_GPO(GPIO_67, HIGH), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version; @@ -30,6 +41,9 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) if (board_version < 2) { *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram); return bid_1_gpio_set_stage_ram; + } else if (board_version == 2) { + *size = ARRAY_SIZE(bid_2_gpio_set_stage_ram); + return bid_2_gpio_set_stage_ram; } *size = 0; |