summaryrefslogtreecommitdiffstats
path: root/src/mainboard/google/zork/variants/gumboz/overridetree.cb
diff options
context:
space:
mode:
authorKevin Chiu <kevin.chiu.17802@gmail.com>2021-04-14 10:46:15 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-04-15 07:30:59 +0000
commitfde6b65b5235cc4ddda5c215056a09aad240fa0e (patch)
tree17e3e977b2fad3ee21d318207c63095603095404 /src/mainboard/google/zork/variants/gumboz/overridetree.cb
parent51f3b3225504707ce6df81b12e373ce8ff1ee58c (diff)
downloadcoreboot-fde6b65b5235cc4ddda5c215056a09aad240fa0e.tar.gz
coreboot-fde6b65b5235cc4ddda5c215056a09aad240fa0e.tar.bz2
coreboot-fde6b65b5235cc4ddda5c215056a09aad240fa0e.zip
mb/google/zork: fine tune stamp_boost parameter for gumboz
The new discovery from Google & AMD, the value currently used STAPM Time Constant of 1640 is reducing real PPT TSP from the target 4.8W to 4.68W. Furthermore, when using the "default" STAPM Time Constant of 1400, the actual real PPT TSP becomes 4.89W. Operating at this default settings therefore uses a higher real PPT TSP, which results in a significant performance improvement. BUG=b:184902568 BRANCH=zork TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test => pass Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I102c1c5f8215a6c5f7a4451f5731167c32e27c90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52313 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/gumboz/overridetree.cb')
-rw-r--r--src/mainboard/google/zork/variants/gumboz/overridetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/zork/variants/gumboz/overridetree.cb b/src/mainboard/google/zork/variants/gumboz/overridetree.cb
index 7139ac8ec231..5675487c709b 100644
--- a/src/mainboard/google/zork/variants/gumboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/gumboz/overridetree.cb
@@ -12,7 +12,7 @@ chip soc/amd/picasso
register "slow_ppt_limit_mW" = "6000"
register "fast_ppt_limit_mW" = "9000"
register "slow_ppt_time_constant_s" = "5"
- register "stapm_time_constant_s" = "1640"
+ register "stapm_time_constant_s" = "1400"
register "sustained_power_limit_mW" = "4800"
register "telemetry_vddcr_vdd_slope_mA" = "41322"