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authorRaul E Rangel <rrangel@chromium.org>2020-05-20 14:07:41 -0600
committerMartin Roth <martinroth@google.com>2020-05-27 23:18:12 +0000
commitb3c41329fdca84a251c183bbc2b0767978e9d96f (patch)
tree47003eae89ad4f6dd86edb52b1fe203d7e7b14b5 /src/mainboard/google/zork/variants/morphius/gpio.c
parentfc9b8b916f7bc0c6ac1579b915937ed23ea3327a (diff)
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mb/google/zork: Add Picasso based Zork mainboard and variants
This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/morphius/gpio.c')
-rw-r--r--src/mainboard/google/zork/variants/morphius/gpio.c48
1 files changed, 48 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c
new file mode 100644
index 000000000000..ff8fa202fc6b
--- /dev/null
+++ b/src/mainboard/google/zork/variants/morphius/gpio.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <ec/google/chromeec/ec.h>
+
+static const struct soc_amd_gpio morphius_v1_gpio_set_stage_ram[] = {
+ /* USB_OC4_L - USB_A1 */
+ PAD_NF(GPIO_14, USB_OC4_L, PULL_UP),
+ /* USB_OC2_L - USB A0 */
+ PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
+ /* DMIC_AD_EN */
+ PAD_GPO(GPIO_84, HIGH),
+};
+
+static const struct soc_amd_gpio morphius_v2_gpio_set_stage_ram[] = {
+ /* USB_OC4_L - USB_A1 */
+ PAD_NF(GPIO_14, USB_OC4_L, PULL_UP),
+ /* USB_OC2_L - USB A0 */
+ PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
+};
+
+const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
+{
+ uint32_t board_version;
+
+ /*
+ * If board version cannot be read, assume that this is an older revision of the board
+ * and so apply overrides. If board version is provided by the EC, then apply overrides
+ * if version < 2.
+ */
+ if (google_chromeec_cbi_get_board_version(&board_version))
+ board_version = 1;
+
+ if (board_version <= 1) {
+ *size = ARRAY_SIZE(morphius_v1_gpio_set_stage_ram);
+ return morphius_v1_gpio_set_stage_ram;
+ } else if (board_version <= 2) {
+ *size = ARRAY_SIZE(morphius_v2_gpio_set_stage_ram);
+ return morphius_v2_gpio_set_stage_ram;
+ }
+
+ *size = 0;
+ return NULL;
+}