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authorRaul E Rangel <rrangel@chromium.org>2020-05-20 14:07:41 -0600
committerMartin Roth <martinroth@google.com>2020-05-27 23:18:12 +0000
commitb3c41329fdca84a251c183bbc2b0767978e9d96f (patch)
tree47003eae89ad4f6dd86edb52b1fe203d7e7b14b5 /src/mainboard/google/zork/variants/trembyle
parentfc9b8b916f7bc0c6ac1579b915937ed23ea3327a (diff)
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mb/google/zork: Add Picasso based Zork mainboard and variants
This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/trembyle')
-rw-r--r--src/mainboard/google/zork/variants/trembyle/Makefile.inc5
-rw-r--r--src/mainboard/google/zork/variants/trembyle/gpio.c48
-rw-r--r--src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl3
-rw-r--r--src/mainboard/google/zork/variants/trembyle/include/variant/acpi/mainboard.asl3
-rw-r--r--src/mainboard/google/zork/variants/trembyle/include/variant/acpi/sleep.asl3
-rw-r--r--src/mainboard/google/zork/variants/trembyle/include/variant/acpi/thermal.asl3
-rw-r--r--src/mainboard/google/zork/variants/trembyle/include/variant/ec.h3
-rw-r--r--src/mainboard/google/zork/variants/trembyle/include/variant/gpio.h3
-rw-r--r--src/mainboard/google/zork/variants/trembyle/include/variant/thermal.h3
-rw-r--r--src/mainboard/google/zork/variants/trembyle/overridetree.cb162
10 files changed, 236 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/trembyle/Makefile.inc b/src/mainboard/google/zork/variants/trembyle/Makefile.inc
new file mode 100644
index 000000000000..0b6bc4b3494a
--- /dev/null
+++ b/src/mainboard/google/zork/variants/trembyle/Makefile.inc
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+subdirs-y += ../baseboard/spd
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c
new file mode 100644
index 000000000000..7973858d5e34
--- /dev/null
+++ b/src/mainboard/google/zork/variants/trembyle/gpio.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <ec/google/chromeec/ec.h>
+
+static const struct soc_amd_gpio trembyle_v1_v2_gpio_set_stage_ram[] = {
+ /* USB_OC4_L - USB_A1 */
+ PAD_NF(GPIO_14, USB_OC4_L, PULL_UP),
+ /* USB_OC2_L - USB A0 */
+ PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
+ /* DMIC_AD_EN */
+ PAD_GPO(GPIO_84, HIGH),
+};
+
+static const struct soc_amd_gpio trembyle_v3_gpio_set_stage_ram[] = {
+ /* USB_OC4_L - USB_A1 */
+ PAD_NF(GPIO_14, USB_OC4_L, PULL_UP),
+ /* USB_OC2_L - USB A0 */
+ PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
+};
+
+const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
+{
+ uint32_t board_version;
+
+ /*
+ * If board version cannot be read, assume that this is an older revision of the board
+ * and so apply overrides. If board version is provided by the EC, then apply overrides
+ * if version < 2.
+ */
+ if (google_chromeec_cbi_get_board_version(&board_version))
+ board_version = 1;
+
+ if (board_version <= 2) {
+ *size = ARRAY_SIZE(trembyle_v1_v2_gpio_set_stage_ram);
+ return trembyle_v1_v2_gpio_set_stage_ram;
+ } else if (board_version <= 3) {
+ *size = ARRAY_SIZE(trembyle_v3_gpio_set_stage_ram);
+ return trembyle_v3_gpio_set_stage_ram;
+ }
+
+ *size = 0;
+ return NULL;
+}
diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl
new file mode 100644
index 000000000000..900e36f27748
--- /dev/null
+++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/audio.asl>
diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..a1161edb5fdb
--- /dev/null
+++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/mainboard.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/mainboard.asl>
diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/sleep.asl
new file mode 100644
index 000000000000..8177a9df2a8f
--- /dev/null
+++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/sleep.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/sleep.asl>
diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/thermal.asl
new file mode 100644
index 000000000000..7a793d8102ca
--- /dev/null
+++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/thermal.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/thermal.asl>
diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/ec.h b/src/mainboard/google/zork/variants/trembyle/include/variant/ec.h
new file mode 100644
index 000000000000..9e61a440cff2
--- /dev/null
+++ b/src/mainboard/google/zork/variants/trembyle/include/variant/ec.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/ec.h>
diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/gpio.h b/src/mainboard/google/zork/variants/trembyle/include/variant/gpio.h
new file mode 100644
index 000000000000..dfaeec3ae10d
--- /dev/null
+++ b/src/mainboard/google/zork/variants/trembyle/include/variant/gpio.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/thermal.h b/src/mainboard/google/zork/variants/trembyle/include/variant/thermal.h
new file mode 100644
index 000000000000..2af647973d9e
--- /dev/null
+++ b/src/mainboard/google/zork/variants/trembyle/include/variant/thermal.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/thermal.h>
diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
new file mode 100644
index 000000000000..46fada9f5fd8
--- /dev/null
+++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+chip soc/amd/picasso
+
+ # Start : OPN Performance Configuration
+ # See devhub #55593 Chapter 3.2 for documentation
+ # For the below fields, 0 indicates use SOC default
+
+ # System config index
+ register "system_config" = "2"
+
+ # Set STAPM confiuration. All of these fields must be set >0 to take affect
+ register "slow_ppt_limit" = "25000" #mw
+ register "fast_ppt_limit" = "30000" #mw
+ register "slow_ppt_time_constant" = "5" #second
+ register "stapm_time_constant" = "200" #second
+ register "sustained_power_limit" = "15000" #mw
+
+ register "telemetry_vddcr_vdd_slope" = "71222" #mA
+ register "telemetry_vddcr_vdd_offset" = "0"
+ register "telemetry_vddcr_soc_slope" = "28977" #mA
+ register "telemetry_vddcr_soc_offset" = "0"
+
+ # End : OPN Performance Configuration
+
+ # Enable I2C2 for trackpad, touchscreen, pen at 400kHz
+ register "i2c[2]" = "{
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 21, /* 0 to 2.31 (3.3 * .7) */
+ .fall_time_ns = 76, /* 2.31 to 0 */
+ }"
+
+ # Enable I2C3 for H1 400kHz
+ register "i2c[3]" = "{
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 125, /* 0 to 1.26v (1.8 * .7) */
+ .fall_time_ns = 37, /* 1.26v to 0 */
+ .early_init = true,
+ }"
+
+ # See AMD 55570-B1 Table 13: PCI Device ID Assignments.
+ device domain 0 on
+ subsystemid 0x1022 0x1510 inherit
+ device pci 1.6 off end # GPP Bridge 5
+ device pci 1.7 on end # GPP Bridge 6 - NVME
+ device pci 8.1 on # Internal GPP Bridge 0 to Bus A
+ device pci 0.3 on
+ chip drivers/usb/acpi
+ register "desc" = ""Root Hub""
+ register "type" = "UPC_TYPE_HUB"
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 2.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-A Port""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 2.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-A Port""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 2.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(2, 2)"
+ device usb 2.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""User-Facing Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 3.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-A Port""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 3.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-A Port""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 3.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(2, 2)"
+ device usb 3.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""AR Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 3.4 on end
+ end
+ end
+ end
+ end # USB 3.1
+ device pci 0.4 on end # USB 3.1
+ end
+ device pci 14.6 off end # Non-Functional SDHCI
+ end # domain
+
+ device mmio 0xfedc4000 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
+ register "wake" = "22"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""PNP0C50""
+ register "generic.desc" = ""Synaptics Touchpad""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
+ register "generic.wake" = "22"
+ register "generic.probed" = "1"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 2c on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""RAYD0001""
+ register "desc" = ""Raydium Touchscreen""
+ register "probed" = "1"
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+ register "reset_delay_ms" = "20"
+ register "has_power_resource" = "1"
+ device i2c 39 on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "probed" = "1"
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+ register "reset_delay_ms" = "20"
+ register "has_power_resource" = "1"
+ device i2c 10 on end
+ end
+ end
+
+end # chip soc/amd/picasso