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| author | Furquan Shaikh <furquan@google.com> | 2020-06-18 01:34:48 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-06-25 08:08:05 +0000 |
| commit | da459c46bdbb3bb50ef0680d069bf5e47a7d5fad (patch) | |
| tree | 3848c96fdceb44edf03c2ad02b730f82fcef878b /src/mainboard/google/zork/variants/trembyle | |
| parent | c699255ba50ffa3e79dbacb572901e07034662be (diff) | |
| download | coreboot-da459c46bdbb3bb50ef0680d069bf5e47a7d5fad.tar.gz coreboot-da459c46bdbb3bb50ef0680d069bf5e47a7d5fad.tar.bz2 coreboot-da459c46bdbb3bb50ef0680d069bf5e47a7d5fad.zip | |
mb/google/zork: Update ramstage GPIOs for v3 schematics for trembyle reference
This change updates the baseboard GPIO table in ramstage to match v3
version of trembyle reference schematics. All variants using this
reference are accordingly updated to configure the GPIOs that changed
as part of v3 schematics.
BUG=b:157088093, b:154676993, b:157098434
TEST=Compiles
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib1d6ee2e995c1fca229c20ea63da9a45fb89f64a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251393
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/trembyle')
| -rw-r--r-- | src/mainboard/google/zork/variants/trembyle/gpio.c | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c index 7973858d5e34..ce7e5dd5c61e 100644 --- a/src/mainboard/google/zork/variants/trembyle/gpio.c +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -7,20 +7,36 @@ #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> -static const struct soc_amd_gpio trembyle_v1_v2_gpio_set_stage_ram[] = { +static const struct soc_amd_gpio trembyle_bid1_bid2_gpio_set_stage_ram[] = { + /* DMIC_SEL */ + PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), /* USB_OC2_L - USB A0 */ PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + /* EN_PWR_TOUCHPAD_PS2 */ + PAD_GPO(GPIO_67, HIGH), /* DMIC_AD_EN */ PAD_GPO(GPIO_84, HIGH), + /* MST_GPIO_2 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_86, PULL_NONE), + /* MST_GPIO_3 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_90, PULL_NONE), }; -static const struct soc_amd_gpio trembyle_v3_gpio_set_stage_ram[] = { +static const struct soc_amd_gpio trembyle_bid3_gpio_set_stage_ram[] = { + /* DMIC_SEL */ + PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), /* USB_OC2_L - USB A0 */ PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + /* EN_PWR_TOUCHPAD_PS2 */ + PAD_GPO(GPIO_67, HIGH), + /* MST_GPIO_2 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_86, PULL_NONE), + /* MST_GPIO_3 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_90, PULL_NONE), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -36,11 +52,11 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) board_version = 1; if (board_version <= 2) { - *size = ARRAY_SIZE(trembyle_v1_v2_gpio_set_stage_ram); - return trembyle_v1_v2_gpio_set_stage_ram; + *size = ARRAY_SIZE(trembyle_bid1_bid2_gpio_set_stage_ram); + return trembyle_bid1_bid2_gpio_set_stage_ram; } else if (board_version <= 3) { - *size = ARRAY_SIZE(trembyle_v3_gpio_set_stage_ram); - return trembyle_v3_gpio_set_stage_ram; + *size = ARRAY_SIZE(trembyle_bid3_gpio_set_stage_ram); + return trembyle_bid3_gpio_set_stage_ram; } *size = 0; |