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| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2020-12-23 04:42:26 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-25 09:11:17 +0000 |
| commit | 5e0db41602d7e1550d6f669e65dcceb91c291e65 (patch) | |
| tree | 19452901c68d3a379e69390784d5960937d3c279 /src/mainboard/google/zork/variants/vilboz | |
| parent | 3ec3cb82f9ad5d71d19bc461177cca19f9ec6a59 (diff) | |
| download | coreboot-5e0db41602d7e1550d6f669e65dcceb91c291e65.tar.gz coreboot-5e0db41602d7e1550d6f669e65dcceb91c291e65.tar.bz2 coreboot-5e0db41602d7e1550d6f669e65dcceb91c291e65.zip | |
mb/google/zork: adjust the eDP panel power sequence
set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight
on and vary backlight.
BUG=b:171269338
BRANCH=zork
TEST=Build; Verify the UPD was passed to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/zork/variants/vilboz')
| -rw-r--r-- | src/mainboard/google/zork/variants/vilboz/overridetree.cb | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index ddcaf53d3b2a..c3afe1372adb 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -26,6 +26,18 @@ chip soc/amd/picasso # eDP phy tuning settings register "dp_phy_override" = "ENABLE_EDP_TUNINGSET" + # eDP power sequence. all pwr sequence numbers below are in uint of 4ms, + # and "0" as default value + register "edp_pwr_adjust_enable" = "1" + register "pwron_digon_to_de" = "0" + register "pwron_de_to_varybl" = "0" + register "pwrdown_varybloff_to_de" = "0" + register "pwrdown_de_to_digoff" = "0" + register "pwroff_delay" = "0" + register "pwron_varybl_to_blon" = "5" + register "pwrdown_bloff_to_varybloff" = "5" + register "min_allowed_bl_level" = "0" + register "edp_tuningset" = "{ .dp_vs_pemph_level = 0x0, .deemph_6db4 = 0x004b, |