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| author | Furquan Shaikh <furquan@google.com> | 2020-06-24 00:03:06 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-07-01 17:54:51 +0000 |
| commit | 9f47a053a35ea11f0906760bca023f4f99241635 (patch) | |
| tree | affd826774e619f6926a17ee7f7b8296b8b1634d /src/mainboard/google/zork | |
| parent | 7340efcf1998e4197bb2403657efed16e5e4e620 (diff) | |
| download | coreboot-9f47a053a35ea11f0906760bca023f4f99241635.tar.gz coreboot-9f47a053a35ea11f0906760bca023f4f99241635.tar.bz2 coreboot-9f47a053a35ea11f0906760bca023f4f99241635.zip | |
mb/google/zork: Move PCIE_RST1_L deassertion to happen early for dalboz
This change moves PCIE_RST1_L deassertion to happen as part of
variant_pcie_power_reset_configure() instead of
variant_romstage_entry() since romstage is guaranteed to run 100ms+
after PP3300_NVME is enabled. This is one of the first things that
coreboot on x86 does as part of early mainboard configuration.
Additionally, this change also drops deassertion of PCIE_RST0_L on bid
1 for dalboz since PCIE_RST0_L is already deasserted much earlier in
the boot flow.
BUG=b:152582706
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib734aa6ff664268e68388b1997ddce676504f8d2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261996
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Aaron Durbin <adurbin@google.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/zork')
3 files changed, 3 insertions, 27 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 5874e89c069e..c2438768c877 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -268,6 +268,9 @@ __weak void variant_pcie_power_reset_configure(void) { uint32_t board_version; + /* Deassert PCIE_RST1_L */ + gpio_set(GPIO_27, 1); + if (!google_chromeec_cbi_get_board_version(&board_version) && (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)) wifi_power_reset_configure_v3(); diff --git a/src/mainboard/google/zork/variants/dalboz/Makefile.inc b/src/mainboard/google/zork/variants/dalboz/Makefile.inc index a616e2fdc0b8..51d19fe9babb 100644 --- a/src/mainboard/google/zork/variants/dalboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/dalboz/Makefile.inc @@ -2,7 +2,5 @@ subdirs-y += ./spd -romstage-y += romstage.c - ramstage-y += gpio.c ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/dalboz/romstage.c b/src/mainboard/google/zork/variants/dalboz/romstage.c deleted file mode 100644 index 42e36c4525c5..000000000000 --- a/src/mainboard/google/zork/variants/dalboz/romstage.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <stddef.h> -#include <soc/romstage.h> -#include <baseboard/variants.h> -#include <ec/google/chromeec/ec.h> -#include <gpio.h> -#include <soc/gpio.h> -#include <variant/gpio.h> - -void variant_romstage_entry(void) -{ - uint32_t board_version; - - if (google_chromeec_cbi_get_board_version(&board_version)) - board_version = 1; - - if (board_version < 2) { - /* SET PCIE_RST0_L HIGH */ - gpio_set(WIFI_PCIE_RESET_L, 1); - } else { - /* SET PCIE_RST1_L HIGH */ - gpio_set(PCIE_RST1_L, 1); - } -} |