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| author | Ivy Jian <ivy_jian@compal.corp-partner.google.com> | 2020-04-30 10:05:47 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:55:55 +0000 |
| commit | 1d17529954fda73460ef2441706139967e3a6b78 (patch) | |
| tree | fee72c94c6be1260c310aac7269a4e71a1884da6 /src/mainboard/google | |
| parent | ed6eb2713a738c45ab876941d6b5805fd00bf13c (diff) | |
| download | coreboot-1d17529954fda73460ef2441706139967e3a6b78.tar.gz coreboot-1d17529954fda73460ef2441706139967e3a6b78.tar.bz2 coreboot-1d17529954fda73460ef2441706139967e3a6b78.zip | |
mb/google/deltaur: Update USB/WWAN config
Update USB3 ports configuration as schematics design.
BUG=b:155026295
TEST=Boot into OS and check WWAN device detected by lsusb.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40818
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 26 |
1 files changed, 8 insertions, 18 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 498266efdd83..e31c89b4683a 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -48,6 +48,8 @@ chip soc/intel/tigerlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB Port 2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN # PCIe root port 6 (WLAN), clock 1 register "PcieRpEnable[5]" = "1" @@ -232,33 +234,21 @@ chip soc/intel/tigerlake device usb 2.9 on end end chip drivers/usb/acpi - register "desc" = ""Type-C Port 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "desc" = ""Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 3.0 on end end chip drivers/usb/acpi - register "desc" = ""Type-C Port 2"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "desc" = ""Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(2, 1)" device usb 3.1 on end end chip drivers/usb/acpi - register "desc" = ""Type-A Port 1 (Right)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Type-A Port 2 (Left)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.3 on end - end - chip drivers/usb/acpi register "desc" = ""WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device usb 3.4 on end + device usb 3.2 on end end end end @@ -297,7 +287,7 @@ chip soc/intel/tigerlake device pci 1c.0 on end # PCIe Root Port #1 (USB) device pci 1c.1 on end # PCIe Root Port #2 (USB) device pci 1c.2 off end # PCIe Root Port #3 () - device pci 1c.3 on end # PCIe Root Port #4 (WWAN) + device pci 1c.3 off end # PCIe Root Port #4 (WWAN) device pci 1c.4 on end # PCIe Root Port #5 (LTE) device pci 1c.5 on end # PCIe Root Port #6 (WiFi) device pci 1c.6 on end # PCIe Root Port #7 (Card reader) |