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| author | Sukumar Ghorai <sukumar.ghorai@intel.com> | 2023-07-31 18:11:04 -0700 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-05 16:03:37 +0000 |
| commit | c5a7d604c8e61cfc482cd7cb1f4d186d1dddef8f (patch) | |
| tree | 5354e91373ffc3c8fd9ab864748d2447bbd9f09d /src/mainboard/google | |
| parent | 684eca7dd2187346405180425d3537ed48db3c47 (diff) | |
| download | coreboot-c5a7d604c8e61cfc482cd7cb1f4d186d1dddef8f.tar.gz coreboot-c5a7d604c8e61cfc482cd7cb1f4d186d1dddef8f.tar.bz2 coreboot-c5a7d604c8e61cfc482cd7cb1f4d186d1dddef8f.zip | |
mb/google/rex: enable d3hot for storage devices
_DSD "StorageD3Enable" property is needs to be set under the root
port in the DSDT or SSDT. The ACPI _DSD method is the preferred way
to opt D3hot support for storage devices.
This also bypasses the low LTR from SSD that blocking S0i2.2
LTR/latency SoC requirement.
Name (_DSD, Package () {
ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"),
Package () {
Package (2) {"StorageD3Enable", 1},
// 1 - Enable; 0 - Disable
}
}
)
BUG=b:289028958
TEST=Check code compiles & boot rex, and verify the "StorageD3Enable"
SSDT entry.
Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76835
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/overridetree.cb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 0cbea7b052fd..5c7958a72fa1 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -303,6 +303,13 @@ chip soc/intel/meteorlake .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" + register "srcclk_pin" = "4" + device generic 0 on end + end end #PCIE9 SSD card device ref ish on probe ISH ISH_ENABLE |