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| author | Martin Roth <martinroth@chromium.org> | 2021-04-05 17:24:51 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-07 22:50:18 +0000 |
| commit | d76b4f6607ba233358b7eb481d098b3abbaafedb (patch) | |
| tree | f5654f7bb7d2c23932fe75d30b373c8d213ab1f6 /src/mainboard/google | |
| parent | fdf2fb78b5c6caedce3290fc00b00c333d72c153 (diff) | |
| download | coreboot-d76b4f6607ba233358b7eb481d098b3abbaafedb.tar.gz coreboot-d76b4f6607ba233358b7eb481d098b3abbaafedb.tar.bz2 coreboot-d76b4f6607ba233358b7eb481d098b3abbaafedb.zip | |
mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptors
pcie_rst isn't working correctly, so use the AUX resets to reset the
PCIe devices before training.
BUG=b:182202136
TEST=See PCIe devices train & enumerate
Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/guybrush/port_descriptors.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index b0f4fa9ba981..322781238d92 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/platform_descriptors.h> +#include <soc/gpio.h> #include <types.h> /* TODO: test if this really works */ @@ -14,6 +15,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .function_number = 1, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, + .gpio_group_id = GPIO_29, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* SD */ @@ -25,6 +27,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .function_number = 2, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, + .gpio_group_id = GPIO_70, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* WWAN */ @@ -36,6 +39,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .function_number = 3, .turn_off_unused_lanes = true, .clk_req = CLK_REQ2, + .gpio_group_id = GPIO_18, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* NVME */ @@ -47,6 +51,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .function_number = 4, .turn_off_unused_lanes = true, .clk_req = CLK_REQ3, + .gpio_group_id = GPIO_40, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} } }; |