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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-11-14 08:09:02 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-11-14 17:53:20 +0100 |
| commit | ff73306ec2612f11d408bf9d708153bb45975ad3 (patch) | |
| tree | 4b28c00b77a5953013b8e78970025819174e3930 /src/mainboard/hp/dl165_g6_fam10 | |
| parent | c1928e2872aa0ae84043b33bdc863ff712f79871 (diff) | |
| download | coreboot-ff73306ec2612f11d408bf9d708153bb45975ad3.tar.gz coreboot-ff73306ec2612f11d408bf9d708153bb45975ad3.tar.bz2 coreboot-ff73306ec2612f11d408bf9d708153bb45975ad3.zip | |
Use mainboard hook for HP DL165
The board incorrectly overrides the southbridge hook, so use the
new mainboard hook instead. This change also activates the actual
southbridge hook to enable decode of complete 4 MB flash memory region.
Change-Id: I02c6fe89ae9ad4a7403f024fac875ebd88a8e142
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1831
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/hp/dl165_g6_fam10')
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/bootblock.c | 8 |
2 files changed, 8 insertions, 2 deletions
diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index cdff24f868b0..43c42439e2f2 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -90,7 +90,7 @@ config HEAP_SIZE hex default 0xc0000 -config BOOTBLOCK_SOUTHBRIDGE_INIT +config BOOTBLOCK_MAINBOARD_INIT string default "mainboard/hp/dl165_g6_fam10/bootblock.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index 2c56c4ccf5db..479e0b6bcebc 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -18,6 +18,9 @@ static inline void shc4307_exit_ext_func_mode(device_t dev) #define DBG_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x3) #define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa) +/* FIXME: This appears to be a super-io initialisation, + * placed in the mainboard directory. + */ void shc4307_init(void) { shc4307_enter_ext_func_mode(CMOS_DEV); @@ -43,6 +46,9 @@ void shc4307_init(void) shc4307_exit_ext_func_mode(CMOS_DEV); } -static void bootblock_southbridge_init(void) { +static void bootblock_mainboard_init(void) +{ + bootblock_northbridge_init(); + bootblock_southbridge_init(); shc4307_init(); } |