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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-12 17:37:42 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-23 10:59:15 +0000 |
| commit | d99b693c965abb13aa57c5701bfd08547fa93cb5 (patch) | |
| tree | 0f71b7e99c13491b2f49da0ffa450be92b2873b2 /src/mainboard/hp | |
| parent | 8d529421d3d72b4050c4c26c31dea280f53d1326 (diff) | |
| download | coreboot-d99b693c965abb13aa57c5701bfd08547fa93cb5.tar.gz coreboot-d99b693c965abb13aa57c5701bfd08547fa93cb5.tar.bz2 coreboot-d99b693c965abb13aa57c5701bfd08547fa93cb5.zip | |
nb/intel/haswell: Confine `pei_data` uses to raminit.c
Reorganize romstage.c to resemble sandybridge, and move everything that
needs `pei_data` into raminit.c function `perform_raminit`. Barring USB
settings, coreboot code no longer depends on pei_data.h definitions. It
still depends on MRC, though. For now.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I433f88db5fe7a7533ab6837015647ec31fb45e88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51449
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/hp')
0 files changed, 0 insertions, 0 deletions