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authorMeera Ravindranath <meera.ravindranath@intel.com>2021-09-06 21:21:34 +0530
committerNick Vaccaro <nvaccaro@google.com>2021-10-04 19:49:38 +0000
commit94a03fff07750e0c37f8ba6b0463c79f80372478 (patch)
tree61afb95d479d6cd7b47dd776d48e861a52b07f87 /src/mainboard/intel/adlrvp/devicetree_m.cb
parent126162c38f47cab8569cae70373d5b512e071c14 (diff)
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mb/intel/adlrvp{p,m}: Enable dynamic GPIO PM
GPIO PM was disabled for adlrvp to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot adlrvp to OS, ensure no TPM timeout errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/devicetree_m.cb')
-rw-r--r--src/mainboard/intel/adlrvp/devicetree_m.cb9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 5d24a420c75d..1a8c641ae331 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -10,15 +10,6 @@ chip soc/intel/alderlake
device lapic 0 on end
end
- # This disables autonomous GPIO power management, otherwise
- # old cr50 FW only supports short pulses.
- register "gpio_override_pm" = "1"
- register "gpio_pm[COMM_0]" = "0"
- register "gpio_pm[COMM_1]" = "0"
- register "gpio_pm[COMM_2]" = "0"
- register "gpio_pm[COMM_4]" = "0"
- register "gpio_pm[COMM_5]" = "0"
-
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE