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| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2021-06-15 17:26:31 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-17 17:05:58 +0000 |
| commit | b10afbd2e2a8326fb21dc726a6c2bd53b06eb010 (patch) | |
| tree | 84ccad4d25ce713d2733eb8b0e6a6815f65627b6 /src/mainboard/intel/adlrvp/devicetree_m.cb | |
| parent | e4aa07e2bda92b7beacc5b1cd7ca88cefde0f531 (diff) | |
| download | coreboot-b10afbd2e2a8326fb21dc726a6c2bd53b06eb010.tar.gz coreboot-b10afbd2e2a8326fb21dc726a6c2bd53b06eb010.tar.bz2 coreboot-b10afbd2e2a8326fb21dc726a6c2bd53b06eb010.zip | |
mb/intel/adlrvp_m: Configure DP_HPD as PAD_NC and disable DdiPortHpd
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1), this causes redundancy with legacy HPD interruption.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=None
TEST=Boot to kernel and verified no kernel HPD pins assertion message.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/devicetree_m.cb')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_m.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index ae248429a9d0..4d32ce9135a8 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -86,6 +86,10 @@ chip soc/intel/alderlake [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" + # Disable DDI ports HPD + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + # TCSS USB3 register "TcssAuxOri" = "0" |