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| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2021-06-17 11:56:16 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-17 20:45:55 +0000 |
| commit | d4e19bfaba47bfcdc7b0a3ab8b9989bb07f81a20 (patch) | |
| tree | 66095a8ea50e9a2297cdd253645469a3e9d8e1c2 /src/mainboard/intel/adlrvp/devicetree_m.cb | |
| parent | 57bc814ea1166c5c86781e6f8d93ca2ab85c2aa9 (diff) | |
| download | coreboot-d4e19bfaba47bfcdc7b0a3ab8b9989bb07f81a20.tar.gz coreboot-d4e19bfaba47bfcdc7b0a3ab8b9989bb07f81a20.tar.bz2 coreboot-d4e19bfaba47bfcdc7b0a3ab8b9989bb07f81a20.zip | |
mb/intel/adlrvp_m: Remove DP_HPD 1 & 2 definition from devicetree
Due to latest corresponding UPD filling implementation, this is not
required.
This patch fixed the brokenness caused by
Commit hash b10afbd2e2a8326fb21dc726a6c2bd53b06eb010.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp/devicetree_m.cb')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_m.cb | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 4d32ce9135a8..ae248429a9d0 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -86,10 +86,6 @@ chip soc/intel/alderlake [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" - # Disable DDI ports HPD - register "DdiPort1Hpd" = "0" - register "DdiPort2Hpd" = "0" - # TCSS USB3 register "TcssAuxOri" = "0" |