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| author | Subrata Banik <subrata.banik@intel.com> | 2021-02-20 13:52:52 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-22 07:26:14 +0000 |
| commit | 40f53f4b8790c72247901d05e4369ca3e04b28f8 (patch) | |
| tree | c2955430aec95fd28fd05cd73151fff0eb3c5678 /src/mainboard/intel/adlrvp/romstage_fsp_params.c | |
| parent | cbcae2744abcc38296106ff87897a5c02f267989 (diff) | |
| download | coreboot-40f53f4b8790c72247901d05e4369ca3e04b28f8.tar.gz coreboot-40f53f4b8790c72247901d05e4369ca3e04b28f8.tar.bz2 coreboot-40f53f4b8790c72247901d05e4369ca3e04b28f8.zip | |
mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17
Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/romstage_fsp_params.c')
| -rw-r--r-- | src/mainboard/intel/adlrvp/romstage_fsp_params.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index c95d469a7cb5..6ae5c1761066 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -57,7 +57,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) break; case ADL_P_LP4_1: case ADL_P_LP4_2: - case ADL_P_LP5: + case ADL_P_LP5_1: + case ADL_P_LP5_2: memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated); break; default: |