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| author | Furquan Shaikh <furquan@google.com> | 2020-12-31 22:50:14 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2021-01-25 19:14:19 +0000 |
| commit | a1c247b55dfc182b365ac0630fc615277017631e (patch) | |
| tree | 9b5c198f570b726e9bbe70cce9a14ddb910f2f42 /src/mainboard/intel/adlrvp/romstage_fsp_params.c | |
| parent | 13d6a4647d3c46db88a295bfa6cf45608ada8a9d (diff) | |
| download | coreboot-a1c247b55dfc182b365ac0630fc615277017631e.tar.gz coreboot-a1c247b55dfc182b365ac0630fc615277017631e.tar.bz2 coreboot-a1c247b55dfc182b365ac0630fc615277017631e.zip | |
soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver
This change uses the newly added meminit block driver and updates ADL
SoC and mainboard code accordingly.
BUG=b:172978729
Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/romstage_fsp_params.c')
| -rw-r--r-- | src/mainboard/intel/adlrvp/romstage_fsp_params.c | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 2f03cb4e84a2..50ba1b3c0503 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -31,19 +31,21 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) int board_id = get_board_id(); const bool half_populated = false; - const struct spd_info lp4_lp5_spd_info = { - .read_type = READ_SPD_CBFS, - .spd_spec.spd_index = get_spd_index(), + const struct mem_spd lp4_lp5_spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, + .cbfs_index = get_spd_index(), }; - const struct spd_info ddr4_ddr5_spd_info = { - .read_type = READ_SMBUS, - .spd_spec = { - .spd_smbus_address = { - [0] = 0xa0, - [1] = 0xa2, - [8] = 0xa4, - [9] = 0xa6, + const struct mem_spd ddr4_ddr5_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0xa0, + .addr_dimm[1] = 0xa2, + }, + [1] = { + .addr_dimm[0] = 0xa4, + .addr_dimm[1] = 0xa6, }, }, }; |