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| author | Subrata Banik <subrata.banik@intel.com> | 2021-06-04 16:47:19 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-06-05 19:54:43 +0000 |
| commit | 2cfb83fcf360b8d688f003eeb557111c5961e312 (patch) | |
| tree | 21f3d8bd13b7d13a2dc0cdd1ca94a172a5aaa6d0 /src/mainboard/intel/adlrvp/variants | |
| parent | c000057aa60f710c2b515f6a0e86fb407e2686d8 (diff) | |
| download | coreboot-2cfb83fcf360b8d688f003eeb557111c5961e312.tar.gz coreboot-2cfb83fcf360b8d688f003eeb557111c5961e312.tar.bz2 coreboot-2cfb83fcf360b8d688f003eeb557111c5961e312.zip | |
mb/intel/adlrvp: Use device aliases
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
different adlrvp boards.
TEST=Dump devicetree device enable list without and with this CL, no
difference observed.
Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55205
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp/variants')
| -rw-r--r-- | src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb index 68a1bfa1d60f..133a737f661e 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb @@ -1,13 +1,13 @@ chip soc/intel/alderlake device domain 0 on - device pci 1f.0 on + device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] device pnp 0c09.0 on end end - end # eSPI - device pci 1f.2 hidden + end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -29,6 +29,6 @@ chip soc/intel/alderlake end end end - end # PMC + end end end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb index 9130a126a19c..bfc899110e97 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -1,15 +1,15 @@ chip soc/intel/alderlake device domain 0 on - device pci 1f.0 on + device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] use conn1 as mux_conn[1] use conn2 as mux_conn[2] device pnp 0c09.0 on end end - end # eSPI - device pci 1f.2 hidden + end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -37,6 +37,6 @@ chip soc/intel/alderlake end end end - end # PMC + end end end |