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authorMaxim Polyakov <max.senia.poliak@gmail.com>2020-07-26 12:30:54 +0300
committerPatrick Georgi <pgeorgi@google.com>2020-08-03 05:23:27 +0000
commitc8b7215639bcb5f3812bc33fe93b537ede15bad0 (patch)
treeaef060bb7955757140e05c55e71aba9ba16204ff /src/mainboard/intel/cedarisland_crb
parenta64748c2020a55e498842d87d032a6834e73be64 (diff)
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mb/intel/cedarisland: Use FSP_M_CONFIG structure to set UPD
According to src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h, use FSP_M_CONFIG structure fields to configure UPD options for FSP-M in romstage instead of raw offsets. Change-Id: Idb25d8954b09805b496ab97b341a8ef1ac38bb6a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/cedarisland_crb')
-rw-r--r--src/mainboard/intel/cedarisland_crb/romstage.c21
1 files changed, 5 insertions, 16 deletions
diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c
index e82d26b1e168..84686054848c 100644
--- a/src/mainboard/intel/cedarisland_crb/romstage.c
+++ b/src/mainboard/intel/cedarisland_crb/romstage.c
@@ -1,25 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/mmio.h>
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
- void *start = (void *) m_cfg;
- // BoardId
- write8(start + 140, 0x1d);
-
- // BoardTypeBitmask
- write32(start + 104, 0x11111111);
-
- // DebugPrintLevel
- write8(start + 45, 8);
-
- // KtiLinkSpeedMode
- write8(start + 64, 0);
-
- // KtiPrefetchEn
- write8(start + 53, 2);
+ m_cfg->BoardId = 0x1d;
+ m_cfg->BoardTypeBitmask = 0x11111111;
+ m_cfg->DebugPrintLevel = 8;
+ m_cfg->KtiLinkSpeedMode = 0;
+ m_cfg->KtiPrefetchEn = 2;
}