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| author | Marc Jones <marcjones@sysproconsulting.com> | 2021-03-09 12:14:06 -0700 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2021-03-20 16:00:54 +0000 |
| commit | f332e47f5696335de2167b6163de0cdbfe63df92 (patch) | |
| tree | ca53ac5ae1a01159320502ef16087e4fc8ca75c5 /src/mainboard/intel/cedarisland_crb | |
| parent | f479c85227f530e48d68cf00b9a4bf249bbc2945 (diff) | |
| download | coreboot-f332e47f5696335de2167b6163de0cdbfe63df92.tar.gz coreboot-f332e47f5696335de2167b6163de0cdbfe63df92.tar.bz2 coreboot-f332e47f5696335de2167b6163de0cdbfe63df92.zip | |
mainboard/: Register chipset_lockdown on xeon_sp mainboards
Set chipset_lockdown in devicetree for recommended security settings.
Change-Id: Ie27450dd32463243b1456932a1d39d40afa81da1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51388
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/cedarisland_crb')
| -rw-r--r-- | src/mainboard/intel/cedarisland_crb/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/intel/cedarisland_crb/devicetree.cb b/src/mainboard/intel/cedarisland_crb/devicetree.cb index a82f022c0b47..4691c0541b84 100644 --- a/src/mainboard/intel/cedarisland_crb/devicetree.cb +++ b/src/mainboard/intel/cedarisland_crb/devicetree.cb @@ -1,4 +1,9 @@ chip soc/intel/xeon_sp/cpx + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device cpu_cluster 0 on device lapic 0 on end end |