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| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-07-19 02:05:08 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-07-29 05:18:54 +0000 |
| commit | 2597dc10d61f03ef336a86d190d8c906e8e12ef3 (patch) | |
| tree | 5cef8fd6d34b1fd0d28c96455a1ea52e04f88473 /src/mainboard/intel/elkhartlake_crb | |
| parent | 471dca7b107d7d1b2e6d6b186f14ba2f23a90215 (diff) | |
| download | coreboot-2597dc10d61f03ef336a86d190d8c906e8e12ef3.tar.gz coreboot-2597dc10d61f03ef336a86d190d8c906e8e12ef3.tar.bz2 coreboot-2597dc10d61f03ef336a86d190d8c906e8e12ef3.zip | |
mb/intel/ehlcrb: Select LPSS console by default
Select `INTEL_LPSS_UART_FOR_CONSOLE` to allow using PCH UART 2 as
coreboot console. Also, simplify `UART_FOR_CONSOLE` defaults.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I853777116fc541e5dc31f3ca8673f8bf66c7c9e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/elkhartlake_crb')
| -rw-r--r-- | src/mainboard/intel/elkhartlake_crb/Kconfig | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig b/src/mainboard/intel/elkhartlake_crb/Kconfig index 0f880b577612..153bfd2a6f1c 100644 --- a/src/mainboard/intel/elkhartlake_crb/Kconfig +++ b/src/mainboard/intel/elkhartlake_crb/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_SPD_IN_CBFS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE select SOC_INTEL_ELKHARTLAKE config MAINBOARD_DIR @@ -40,7 +41,6 @@ config VBOOT config UART_FOR_CONSOLE int - default 2 if INTEL_LPSS_UART_FOR_CONSOLE - default 0 + default 2 endif |