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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2015-05-18 10:29:06 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2015-05-27 22:23:05 +0200 |
| commit | 0e90dae584c506b06e7bf3d89064a64db04132bb (patch) | |
| tree | 83876d4f6e39e432789c0bcdb6384068bdcd566b /src/mainboard/intel/emeraldlake2 | |
| parent | 40772a0b5afc7d82a213b005905e2d9e71a6328e (diff) | |
| download | coreboot-0e90dae584c506b06e7bf3d89064a64db04132bb.tar.gz coreboot-0e90dae584c506b06e7bf3d89064a64db04132bb.tar.bz2 coreboot-0e90dae584c506b06e7bf3d89064a64db04132bb.zip | |
Move TPM code out of chromeos
This code is not specific to ChromeOS and is useful outside of it.
Like with small modifications it can be used to disable TPM altogether.
Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10269
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/emeraldlake2')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/romstage.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index c9d5cf1f78c7..bcf498b7a44d 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -39,10 +39,8 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> +#include <tpm.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif #define SIO_PORT 0x164e @@ -255,8 +253,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(boot_mode == 2); + } timestamp_add_now(TS_END_ROMSTAGE); } |