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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-05-30 15:01:06 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-31 22:11:51 +0200 |
| commit | bc518d5cab4234a0d0d06a7d3829bbca9e318ba6 (patch) | |
| tree | 09eb5cf6c3476c17ca34fde7164d14c2f2ec3b0b /src/mainboard/intel/galileo/gen1.h | |
| parent | ac78db3a53a7653a73409936455d68c754291e9d (diff) | |
| download | coreboot-bc518d5cab4234a0d0d06a7d3829bbca9e318ba6.tar.gz coreboot-bc518d5cab4234a0d0d06a7d3829bbca9e318ba6.tar.bz2 coreboot-bc518d5cab4234a0d0d06a7d3829bbca9e318ba6.zip | |
quark: Enable HSUART0 as console
The use of HSUART0 on galileo requires early initialization of the I2C
GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1
on the expansion connector.
TEST=None
Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15010
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/galileo/gen1.h')
| -rw-r--r-- | src/mainboard/intel/galileo/gen1.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h index e1e8f5907014..23b23091d2ee 100644 --- a/src/mainboard/intel/galileo/gen1.h +++ b/src/mainboard/intel/galileo/gen1.h @@ -59,6 +59,56 @@ static const struct reg_script gen1_gpio_init[] = { REG_SCRIPT_END }; +static const struct reg_script gen1_hsuart0_0x20[] = { + /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1 + * Set IO1_MUX (EXP.PORT3_5) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT5), + + /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD + * Set IO0_MUX (EXP.PORT3_4) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT4), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT4), + + REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2), + REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2), + REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2), + + REG_SCRIPT_END +}; + +static const struct reg_script gen1_hsuart0_0x21[] = { + /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1 + * Set IO1_MUX (EXP.PORT3_5) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT5), + + /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD + * Set IO0_MUX (EXP.PORT3_4) output, low + * Set LVL_OE (GPIO_SUS2) output, high + */ + REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT4), + REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT4), + + REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2), + REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2), + REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2), + + REG_SCRIPT_END +}; + static const struct reg_script gen1_i2c_0x20_init[] = { /* Route I2C pins to Arduino header: * Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector |