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author | Hannah Williams <hannah.williams@intel.com> | 2017-05-05 16:39:21 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-26 20:31:24 +0000 |
commit | d59f62bbdabeb98f12896c6af0ef50cbf25e013f (patch) | |
tree | ee22acd54dce71c326c019ee41f86c310f2b0df6 /src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h | |
parent | 50ab84fa370ac247dfe57a65f9d9b1ed0384e7fa (diff) | |
download | coreboot-d59f62bbdabeb98f12896c6af0ef50cbf25e013f.tar.gz coreboot-d59f62bbdabeb98f12896c6af0ef50cbf25e013f.tar.bz2 coreboot-d59f62bbdabeb98f12896c6af0ef50cbf25e013f.zip |
mainboard/intel/glkrvp: Add support for GLKRVP
GLKRVP is a reference board for GLK SOC
RVP1 has DDR4 and RVP2 has LPDDR4
RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected
if building for RVP1
GLKRVP can work with internal Intel EC or external Chrome EC AIC.
For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected (
CONFIG_GLK_INTEL_EC should be selected for internal EC config)
By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC
config.
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Reviewed-on: https://review.coreboot.org/19604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h')
-rw-r--r-- | src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 000000000000..c278cdee26b0 --- /dev/null +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_VARIANTS_H +#define BASEBOARD_VARIANTS_H + +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Return the board id for the current variant board. */ +uint8_t variant_board_id(void); + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_sleep_gpio_table(size_t *num); + +/* Baseboard default swizzle. Can be reused if swizzle is same. */ +extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle; +/* Return LPDDR4 configuration structure. */ +const struct lpddr4_cfg *variant_lpddr4_config(void); +/* Return memory SKU for the board. */ +size_t variant_memory_sku(void); + +/* Return ChromeOS gpio table and fill in number of entries. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); + +/* Seed the NHLT tables with the board specific information. */ +struct nhlt; +void variant_nhlt_init(struct nhlt *nhlt); + +#endif /* BASEBOARD_VARIANTS_H */ |