soc/intel/icelake: Update GPIOs for Icelake SOC

This implementation updates the GPIO pins, communities and
group mapping.

Change details:

1. Update 5 GPIO community includes 11 GPIO groups
   GPIO COM 0
     GPP_G, GPP_B, GPP_A
   GPIO COM 1
     GPP_H, GPP_D, GPP_F
   GPIO COM 2
     GPD
   GPIO COM 4
     GPP_C, GPP_E
   GPIO COM 5
     GPP_R, GPP_S

2. Update GPIO IRQ routing.

3. Add GPIO configuration for iclrvp board.

Change-Id: I223abacc18f78631a42f340952f13d45fa9a4703
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>

1 files changed, 18 insertions, 0 deletions

diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc
new file mode 100644
index 000000000000..0c1af6998505
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c