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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2020-09-28 19:36:56 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-29 03:48:27 +0000 |
| commit | 258ceb75074ed47d221bad0a4ebae805deb185ed (patch) | |
| tree | 86f3092a17d1bf324f24b79070772f6dbb5ffca0 /src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | |
| parent | 823e73e143197a7ee3df247398587ea86ab6dcfa (diff) | |
| download | coreboot-258ceb75074ed47d221bad0a4ebae805deb185ed.tar.gz coreboot-258ceb75074ed47d221bad0a4ebae805deb185ed.tar.bz2 coreboot-258ceb75074ed47d221bad0a4ebae805deb185ed.zip | |
mb/intel/jslrvp: Update PMC as hidden device
This change allows treating the PMC as a 'hidden' PCI device on
JasperLake, so that the MMIO & I/O resources can be exposed as
belonging to this device, instead of the system agent and LPC/eSPI.
Original patch for jasperlake SoC here:
CB:42018
This change was missing for JasperLake rvp board.
TEST=Checked PMC init function is called and also checked PCI resource
for PMC device 1f.2.
Change-Id: I7531d32c62d3f9735938f744f2892ab9c9bebddf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index f8fea47aa577..fc96719643ce 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -466,7 +466,7 @@ chip soc/intel/jasperlake end # GSPI #1 device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI |