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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2020-03-30 20:15:01 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-04-21 05:48:21 +0000 |
| commit | ef5ff0b49a5d61b8dfc313fdddba3f07e3f7a8fc (patch) | |
| tree | 850d9d0f79ed4bf2834adbd1a5db6bb9021e4dc2 /src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | |
| parent | aa832c19b2c3e4f1be6b917abd962a7d664be7a3 (diff) | |
| download | coreboot-ef5ff0b49a5d61b8dfc313fdddba3f07e3f7a8fc.tar.gz coreboot-ef5ff0b49a5d61b8dfc313fdddba3f07e3f7a8fc.tar.bz2 coreboot-ef5ff0b49a5d61b8dfc313fdddba3f07e3f7a8fc.zip | |
mb/intel/jasperlake_rvp: Enable Wifi and BT
Enable Wifi and Bluetooth for Jasper Lake RVP with following changes:
1. Enable related pci root ports for WLAN and BT
2. Disable unused root ports and clkreq for unused clocks
3. Configure GPIOs properly for M.2 port
BUG=None
BRANCH=None
TEST=Code compiles and able to detect Wifi/BT module on board.
Change-Id: Ifbd07022c05769c04ecd49c81a4430947125b32a
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39933
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index b632b7804ce4..7dc45ae52009 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -63,22 +63,19 @@ chip soc/intel/jasperlake register "PchHdaAudioLinkDmicEnable[1]" = "1" # PCIe port 1 for M.2 E-key WLAN - register "PcieRpEnable[1]" = "1" - - # RP 1 uses CLK SRC 1 - register "PcieClkSrcUsage[1]" = "0x01" - - # ClkReq-to-ClkSrc mapping for CLK SRC 1 - register "PcieClkSrcClkReq[1]" = "0x01" - # Enable Root Port 4(x4) for NVMe + register "PcieRpEnable[1]" = "1" register "PcieRpEnable[4]" = "1" - # RP 4 uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "0x04" + register "PcieClkSrcUsage[1]" = "0x01" - # ClkReq-to-ClkSrc mapping for CLK SRC 0 register "PcieClkSrcClkReq[0]" = "0x00" + register "PcieClkSrcClkReq[1]" = "0x01" + register "PcieClkSrcClkReq[2]" = "0x02" + register "PcieClkSrcClkReq[3]" = "0x03" + register "PcieClkSrcClkReq[4]" = "0x04" + register "PcieClkSrcClkReq[5]" = "0x05" register "SataEnable" = "0" @@ -285,12 +282,12 @@ chip soc/intel/jasperlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 on end # PCI Express Port 2 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 device pci 1e.0 on end # UART #0 |