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| author | Sugnan Prabhu S <sugnan.prabhu.s@intel.com> | 2020-08-21 18:13:10 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-26 07:31:11 +0000 |
| commit | 149b2dcb465ad70b5392d70ed2fccfd149df0fce (patch) | |
| tree | f251b6fe375893bb9b5fcb20f0d0fe680d21b487 /src/mainboard/intel/jasperlake_rvp | |
| parent | 65993e8233f8bb54cb4d6967d018f8c97ba8a4fc (diff) | |
| download | coreboot-149b2dcb465ad70b5392d70ed2fccfd149df0fce.tar.gz coreboot-149b2dcb465ad70b5392d70ed2fccfd149df0fce.tar.bz2 coreboot-149b2dcb465ad70b5392d70ed2fccfd149df0fce.zip | |
mb/intel/jasperlake_rvp: Configure GPIO pad to enable I2C4
Includes changes related to GPIO pad to configure I2C4 required for UFC
Change-Id: Ica3ac31f10214b8aff3bb64a2c3b42ccfa28bdcd
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/mainboard/intel/jasperlake_rvp')
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/mainboard.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/mainboard.c b/src/mainboard/intel/jasperlake_rvp/mainboard.c index 3b9dff990a05..315d47d2b0a1 100644 --- a/src/mainboard/intel/jasperlake_rvp/mainboard.c +++ b/src/mainboard/intel/jasperlake_rvp/mainboard.c @@ -3,10 +3,14 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <device/device.h> +#include <intelblocks/pcr.h> #include <soc/gpio.h> +#include <soc/pcr_ids.h> #include <smbios.h> #include <vendorcode/google/chromeos/chromeos.h> +#define SERIAL_IO_PCR_GPPRVRW4 0x60C + static void mainboard_init(void *chip_info) { const struct pad_config *pads; @@ -14,6 +18,9 @@ static void mainboard_init(void *chip_info) pads = variant_gpio_table(&num); gpio_configure_pads(pads, num); + + if (CONFIG(DRIVERS_INTEL_MIPI_CAMERA)) + pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8); } static void mainboard_enable(struct device *dev) |