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| author | Subrata Banik <subratabanik@google.com> | 2022-01-03 18:07:13 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-01-16 13:33:14 +0000 |
| commit | a0d9ad322fe603d4d4cbccda9c7edcfbf0b13409 (patch) | |
| tree | 669b42cd23e87dd8dd89009173d820057afea520 /src/mainboard/intel/kblrvp/Kconfig | |
| parent | 98ce39dce48d9f4b88fb0d71af654f4ed948ea9b (diff) | |
| download | coreboot-a0d9ad322fe603d4d4cbccda9c7edcfbf0b13409.tar.gz coreboot-a0d9ad322fe603d4d4cbccda9c7edcfbf0b13409.tar.bz2 coreboot-a0d9ad322fe603d4d4cbccda9c7edcfbf0b13409.zip | |
soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` config
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel/kblrvp/Kconfig')
| -rw-r--r-- | src/mainboard/intel/kblrvp/Kconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 2abf8329f6e3..6b60ac46eae4 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -31,6 +31,9 @@ config BOARD_INTEL_KBLRVP11 if BOARD_INTEL_KBLRVP_COMMON +config DISABLE_HECI1_AT_PRE_BOOT + default y + config VBOOT select VBOOT_LID_SWITCH |