soc/intel,mb/*: get rid of legacy pad macros

Get rid of legacy pad macros by replacing them with their newer
equivalents.

TEST: TIMELESS-built board images match

Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

4 files changed, 120 insertions, 120 deletions

diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h
index 0417543d31e5..4f7f002bff88 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h
@@ -60,7 +60,7 @@ static const struct pad_config gpio_table[] = {
 /* LPC_CLKRUN */	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 /* EC_LPC_CLK */	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
 /* PCH_LPC_CLK */	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
-/* EC_HID_INT */	PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP),
+/* EC_HID_INT */	PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, DEEP),
 /* ISH_KB_PROX_INT */	PAD_CFG_GPI(GPP_A12, NONE, DEEP),
 /* PCH_SUSPWRACB */	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
 /* PM_SUS_STAT */	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
@@ -72,14 +72,14 @@ static const struct pad_config gpio_table[] = {
 /* GYRO_DRDY */		PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
 /* FLIP_ACCEL_INT */	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
 /* GYRO_INT */		PAD_CFG_GPO(GPP_A22, 1, DEEP),
-/* GPP_A23 */		PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP),
+/* GPP_A23 */		PAD_CFG_GPI_APIC_HIGH(GPP_A23, NONE, DEEP),
 
 /* screen lock */	PAD_CFG_GPI(GPP_B0, NONE, DEEP),
 /* Tch pnl pwren  */	PAD_CFG_GPO(GPP_B1, 1, DEEP),
 /* HSJ_MIC_DET */
 /* BT_RF_kill */	PAD_CFG_GPO(GPP_B3, 1, DEEP),
 /* SNI_DRV_PCH */	PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1),
-/* M.2 BT UART wake */	PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP),
+/* M.2 BT UART wake */	PAD_CFG_GPI_APIC_HIGH(GPP_B5, NONE, DEEP),
 /* WIFI_CLK_REQ */
 /* KEPLR_CLK_REQ */
 /* SRCCLKREQ3# */	/* GPP_B8 */
@@ -88,9 +88,9 @@ static const struct pad_config gpio_table[] = {
 /* MPHY_EXT_PWR_GATE */	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 /* PM_SLP_S0 */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 /* PCH_PLT_RST */	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* GPP_B_14_SPKR */	PAD_CFG_GPI_ACPI_SMI(GPP_B14, NONE, DEEP, YES),
+/* GPP_B_14_SPKR */	PAD_CFG_GPI_SMI(GPP_B14, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* GSPI0_CS# */		/* GPP_B15 */
-/* WLAN_PCIE_WAKE */	PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
+/* WLAN_PCIE_WAKE */	PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* SSD_PCIE_WAKE */	PAD_CFG_GPO(GPP_B17, 1, DEEP),
 /* GSPI0_MOSI */	PAD_CFG_GPO(GPP_B18, 1, DEEP),
 /* CCODEC_SPI_CS */	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
@@ -167,14 +167,14 @@ static const struct pad_config gpio_table[] = {
 /* I2S2_TXD */		PAD_CFG_GPO(GPP_F2, 0, DEEP),
 /* I2S2_RXD */		PAD_CFG_GPO(GPP_F3, 1, DEEP),
 /* I2C2_SDA */		PAD_CFG_GPO(GPP_F4, 0, DEEP),
-/* I2C2_SCL */		PAD_CFG_GPI_APIC(GPP_F5, NONE, DEEP),
+/* I2C2_SCL */		PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, DEEP),
 /* I2C3_SDA */		PAD_CFG_GPO(GPP_F6, 0, DEEP),
 /* I2C3_SCL */		PAD_CFG_GPO(GPP_F7, 0, DEEP),
 /* I2C4_SDA */		PAD_CFG_GPI(GPP_F8, NONE, DEEP),
-/* I2C4_SDA */		PAD_CFG_GPI_APIC(GPP_F9, NONE, DEEP),
+/* I2C4_SDA */		PAD_CFG_GPI_APIC_HIGH(GPP_F9, NONE, DEEP),
 /* AUDIO_IRQ */		PAD_CFG_GPI(GPP_F10, NONE, DEEP),
 /* I2C5_SCL */		PAD_CFG_GPI(GPP_F11, NONE, DEEP),
-/* EMMC_CMD */		PAD_CFG_GPI_ACPI_SCI(GPP_F12, NONE, DEEP, YES),
+/* EMMC_CMD */		PAD_CFG_GPI_SCI(GPP_F12, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* EMMC_DATA0 */	PAD_CFG_GPI(GPP_F13, NONE, DEEP),
 /* EMMC_DATA1 */	PAD_CFG_GPI(GPP_F14, NONE, DEEP),
 /* EMMC_DATA2 */	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
@@ -187,28 +187,28 @@ static const struct pad_config gpio_table[] = {
 /* EMMC_CLK */		PAD_CFG_GPO(GPP_F22, 1, DEEP),
 /* GPP_F23 */
 
-/* SD_CMD */		PAD_CFG_GPI_APIC(GPP_G0, 20K_PD, DEEP),
+/* SD_CMD */		PAD_CFG_GPI_APIC_HIGH(GPP_G0, DN_20K, DEEP),
 /* SD_DATA0 */		PAD_CFG_GPO(GPP_G1, 1, DEEP),
 /* SD_DATA1 */		PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
-/* SD_DATA2 */		PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES),
+/* SD_DATA2 */		PAD_CFG_GPI_SCI(GPP_G3, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* SD_DATA3 */		PAD_CFG_GPO(GPP_G4, 0, DEEP),
 /* SD_CD# */		PAD_CFG_GPO(GPP_G5, 0, DEEP),
 /* SD_CLK */		PAD_CFG_GPO(GPP_G6, 1, DEEP),
-/* SD_WP */		PAD_CFG_GPI_APIC(GPP_G7, NONE, DEEP),
+/* SD_WP */		PAD_CFG_GPI_APIC_HIGH(GPP_G7, NONE, DEEP),
 /* TBD */		PAD_CFG_GPO(GPP_G8, 1, DEEP),
 /* TBD */		PAD_CFG_GPO(GPP_G9, 1, DEEP),
 /* TBD */		PAD_CFG_GPO(GPP_G10, 0, DEEP),
 /* TBD */		PAD_CFG_GPO(GPP_G11, 1, DEEP),
-/* TBD */		PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES),
+/* TBD */		PAD_CFG_GPI_SCI(GPP_G12, DN_20K, DEEP, EDGE_SINGLE, INVERT),
 /* TBD */		PAD_CFG_GPO(GPP_G13, 1, DEEP),
 /* TBD */
 /* TBD */		PAD_CFG_GPO(GPP_G15, 1, DEEP),
 /* TBD */		PAD_CFG_GPO(GPP_G16, 0, DEEP),
 /* TBD */		PAD_CFG_GPO(GPP_G17, 1, DEEP),
-/* TBD */		PAD_CFG_GPI_ACPI_SCI(GPP_G18, NONE, DEEP, YES),
+/* TBD */		PAD_CFG_GPI_SCI(GPP_G18, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* TBD */
 /* TBD */		PAD_CFG_GPO(GPP_G20, 1, DEEP),
-/* TBD */		PAD_CFG_GPI_APIC(GPP_G21, 20K_PD, DEEP),
+/* TBD */		PAD_CFG_GPI_APIC_HIGH(GPP_G21, DN_20K, DEEP),
 /* TBD */		PAD_CFG_GPO(GPP_G22, 1, DEEP),
 /* TBD */		PAD_CFG_GPO(GPP_G23, 1, DEEP),
 
@@ -240,7 +240,7 @@ static const struct pad_config gpio_table[] = {
 /* DDSP_HPD_0 */        PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
 /* DDSP_HPD_1 */        PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
 /* DDSP_HPD_2 */        PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
-/* DDSP_HPD_3 */        PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES),
+/* DDSP_HPD_3 */        PAD_CFG_GPI_SMI(GPP_I3, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* SD_CMD */		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
 /* SD_CMD */		PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
 /* SD_CMD */		PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
index 1ed86b74f96b..e0292cfa86f6 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
@@ -28,35 +28,35 @@
 /* Pad configuration in ramstage. */
 static const struct pad_config gpio_table[] = {
 /* PCH_RCIN */		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
-/* LPC_LAD_0 */		PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1),
-/* LPC_LAD_1 */		PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1),
-/* LPC_LAD_2 */		PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1),
-/* LPC_LAD_3 */		PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1),
+/* LPC_LAD_0 */		PAD_CFG_NF(GPP_A1, DN_20K, DEEP, NF1),
+/* LPC_LAD_1 */		PAD_CFG_NF(GPP_A2, DN_20K, DEEP, NF1),
+/* LPC_LAD_2 */		PAD_CFG_NF(GPP_A3, DN_20K, DEEP, NF1),
+/* LPC_LAD_3 */		PAD_CFG_NF(GPP_A4, DN_20K, DEEP, NF1),
 /* LPC_FRAME */		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
 /* LPC_SERIRQ */	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-/* PM_SLP_S0ix_N */	PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),
+/* PM_SLP_S0ix_N */	PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP),
 /* LPC_CLKRUN */	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
-/* LPC_CLK */		PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
-/* PCH_LPC_CLK */	PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
-/* EC_HID_INT */	PAD_CFG_NC(GPP_A11),
-/* ISH_KB_PROX_INT */	PAD_CFG_NC(GPP_A12),
+/* LPC_CLK */		PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+/* PCH_LPC_CLK */	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+/* EC_HID_INT */	PAD_NC(GPP_A11, NONE),
+/* ISH_KB_PROX_INT */	PAD_NC(GPP_A12, NONE),
 /* PCH_SUSPWRACB */	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
-/* PM_SUS_STAT */	PAD_CFG_NC(GPP_A14),
-/* SUSACK_R_N */	PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
+/* PM_SUS_STAT */	PAD_NC(GPP_A14, NONE),
+/* SUSACK_R_N */	PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
 /* SD_1P8_SEL */	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 /* SD_PWR_EN */		PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
-/* ISH_GP0 */		PAD_CFG_NC(GPP_A18),
-/* ISH_GP1 */		PAD_CFG_NC(GPP_A19),
-/* ISH_GP2 */		PAD_CFG_NC(GPP_A20),
-/* ISH_GP3 */		PAD_CFG_NC(GPP_A21),
-/* ISH_GP4 */		PAD_CFG_NC(GPP_A22),
-/* ISH_GP5 */		PAD_CFG_NC(GPP_A23),
-/* V0.85A_VID0 */	PAD_CFG_NC(GPP_B0),
-/* V0.85A_VID1 */	PAD_CFG_NC(GPP_B1),
+/* ISH_GP0 */		PAD_NC(GPP_A18, NONE),
+/* ISH_GP1 */		PAD_NC(GPP_A19, NONE),
+/* ISH_GP2 */		PAD_NC(GPP_A20, NONE),
+/* ISH_GP3 */		PAD_NC(GPP_A21, NONE),
+/* ISH_GP4 */		PAD_NC(GPP_A22, NONE),
+/* ISH_GP5 */		PAD_NC(GPP_A23, NONE),
+/* V0.85A_VID0 */	PAD_NC(GPP_B0, NONE),
+/* V0.85A_VID1 */	PAD_NC(GPP_B1, NONE),
 /* GP_VRALERTB */	PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP),
-/* TCH_PAD_INTR */	PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
+/* TCH_PAD_INTR */	PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST),
 /* BT_RF_KILL */	PAD_CFG_GPO(GPP_B4, 1, DEEP),
-/* CLK_REQ_SLOT0 */	PAD_CFG_NC(GPP_B5),
+/* CLK_REQ_SLOT0 */	PAD_NC(GPP_B5, NONE),
 /* CLK_REQ_SLOT1 */	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
 /* CLK_REQ_SLOT2 */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
 /* CLK_REQ_SLOT3 */	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
@@ -67,22 +67,22 @@ static const struct pad_config gpio_table[] = {
 /* PCH_PLT_RST */	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 /* TCH_PNL_PWREN */	PAD_CFG_GPO(GPP_B14, 1, DEEP),
 /* GSPI0_CS# */		/* GPP_B15 */
-/* WLAN_PCIE_WAKE */	PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
-/* TBT_CIO */		PAD_CFG_NC(GPP_B17),
-/* SLOT1_WAKE */	PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, DEEP, YES),
+/* WLAN_PCIE_WAKE */	PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT),
+/* TBT_CIO */		PAD_NC(GPP_B17, NONE),
+/* SLOT1_WAKE */	PAD_CFG_GPI_SCI(GPP_B18, UP_20K, DEEP, EDGE_SINGLE, INVERT),
 /* GSPI1_CS */		PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
-/* GSPI1_CLK */		PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1),
-/* GSPI1_MISO */	PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1),
-/* GSPI1_MOSI */	PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
+/* GSPI1_CLK */		PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
+/* GSPI1_MISO */	PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1),
+/* GSPI1_MOSI */	PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
 /* GNSS_RESET */	PAD_CFG_GPO(GPP_B23, 1, DEEP),
 /* SMB_CLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-/* SMB_DATA */		PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
+/* SMB_DATA */		PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
 /* SMBALERT# */		PAD_CFG_GPO(GPP_C2, 1, DEEP),
 /* SML0_CLK */		PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
 /* SML0DATA */		PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-/* SML0ALERT# */	PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST),
+/* SML0ALERT# */	PAD_CFG_GPI_APIC_HIGH(GPP_C5, DN_20K, PLTRST),
 /* SML1_CLK */		PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
-/* SML1_DATA */		PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1),
+/* SML1_DATA */		PAD_CFG_NF(GPP_C7, DN_20K, DEEP, NF1),
 /* UART0_RXD */		PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
 /* UART0_TXD */		PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 /* UART0_RTS */		PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
@@ -91,8 +91,8 @@ static const struct pad_config gpio_table[] = {
 /* UART1_TXD */		PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
 /* UART1_RTS */		PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
 /* UART1_CTS */		PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
-/* I2C0_SDA */		PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
-/* I2C0_SCL */		PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
+/* I2C0_SDA */		PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1),
+/* I2C0_SCL */		PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1),
 /* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 /* I2C1_SCL */		PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
@@ -117,35 +117,35 @@ static const struct pad_config gpio_table[] = {
 /* ISH_UART0_RTS */	PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
 /* ISH_UART0_CTS */	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
 /* DMIC_CLK_1 */	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
-/* DMIC_DATA_1 */	PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1),
+/* DMIC_DATA_1 */	PAD_CFG_NF(GPP_D18, DN_20K, DEEP, NF1),
 /* DMIC_CLK_0 */	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
-/* DMIC_DATA_0 */	PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1),
+/* DMIC_DATA_0 */	PAD_CFG_NF(GPP_D20, DN_20K, DEEP, NF1),
 /* SPI1_D2 */		PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 /* SPI1_D3 */		PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
 /* I2S_MCLK */		PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
-/* SPI_TPM_IRQ */	PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
+/* SPI_TPM_IRQ */	PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST),
 /* SATAXPCIE1 */	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 /* SSD_PEDET */		PAD_CFG_GPI_GPIO_DRIVER(GPP_E2, NONE, DEEP),
 /* EINK_SSR_DFU_N */	PAD_CFG_GPO(GPP_E3, 1, DEEP),
 /* SSD_SATA_DEVSLP */	PAD_CFG_GPO(GPP_E4, 0, DEEP),
 /* SATA_DEVSLP1 */	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
 /* SATA_DEVSLP2 */	/* GPP_E6 */
-/* TCH_PNL_INTR* */	PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
+/* TCH_PNL_INTR* */	PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST),
 /* SATALED# */		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
 /* USB2_OC_0 */		PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 /* USB2_OC_1 */		PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
 /* USB2_OC_2 */		PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
-/* USB2_OC_3 */		PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST),
+/* USB2_OC_3 */		PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, PLTRST),
 /* DDI1_HPD */		PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 /* DDI2_HPD */		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
-/* EC_SMI */		PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
-/* EC_SCI */		PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
+/* EC_SMI */		PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT),
+/* EC_SCI */		PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* EDP_HPD */		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 /* DDPB_CTRLCLK */	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
-/* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
+/* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
 /* DDPC_CTRLCLK */	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
-/* DDPC_CTRLDATA */	PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1),
-/* DDPD_CTRLCLK */	PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
+/* DDPC_CTRLDATA */	PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
+/* DDPD_CTRLCLK */	PAD_CFG_GPI_APIC_HIGH(GPP_E22, NONE, DEEP),
 /* TCH_PNL_RST */	PAD_CFG_GPO(GPP_E23, 1, DEEP),
 /* I2S2_SCLK */		PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
 /* I2S2_SFRM */		PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
@@ -170,7 +170,7 @@ static const struct pad_config gpio_table[] = {
 /* EMMC_DATA7 */	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
 /* EMMC_RCLK */		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 /* EMMC_CLK */		PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
-/* UIM_SIM_DET */	PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP),
+/* UIM_SIM_DET */	PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP),
 /* SD_CMD */		PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
 /* SD_DATA0 */		PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
 /* SD_DATA1 */		PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
@@ -186,7 +186,7 @@ static const struct pad_config gpio_table[] = {
 /* PM_SLP_S3# */	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 /* PM_SLP_S4# */	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 /* PM_SLP_SA# */	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
-/* GPD7 */		PAD_CFG_NC(GPD7),
+/* GPD7 */		PAD_NC(GPD7, NONE),
 /* PM_SUSCLK */		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 /* PCH_SLP_WLAN# */	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 /* PM_SLP_S5# */	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h
index 4ead52c282f0..ff4647f1d213 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h
@@ -48,10 +48,10 @@ static const struct pad_config gpio_table[] = {
 /* PM_SLP_S0ix_R_N*/	PAD_CFG_GPO(GPP_A7, 1, DEEP),
 /* LPC_CLKRUN */	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 /* PCH_CLK_PCI_TPM */	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
-/* PCH_LPC_CLK */	PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP),
+/* PCH_LPC_CLK */	PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, DEEP),
 /* ISH_KB_PROX_INT */	PAD_CFG_GPO(GPP_A12, 1, RSMRST),
 /* PCH_SUSPWRACB */	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
-/* PCH_SUSACK */	PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
+/* PCH_SUSACK */	PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
 /* SD_1P8_SEL */	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 /* SD_PWR_EN */		PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
 /* ACCEL INTERRUPT */	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
@@ -59,33 +59,33 @@ static const struct pad_config gpio_table[] = {
 /* GYRO_DRDY */		PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
 /* FLIP_ACCEL_INT */	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
 /* GYRO_INT */		PAD_CFG_GPO(GPP_A22, 1, DEEP),
-/* ISH_GP5 */		PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP),
+/* ISH_GP5 */		PAD_CFG_GPI_APIC_HIGH(GPP_A23, NONE, DEEP),
 /* CORE_VID0 */		PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
 /* CORE_VID1 */		PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
 /* HSJ_MIC_DET */	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
-/* TRACKPAD_INT */	PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
+/* TRACKPAD_INT */	PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST),
 /* BT_RF_KILL */	PAD_CFG_GPO(GPP_B4, 1, DEEP),
-/* SRCCLKREQ0# */	PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP),
+/* SRCCLKREQ0# */	PAD_CFG_GPI_APIC_HIGH(GPP_B5, NONE, DEEP),
 /* MPHY_EXT_PWR_GATE */	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 /* PM_SLP_S0 */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 /* PCH_PLT_RST */	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* GPP_B_14_SPKR */	PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP),
-/* WLAN_PCIE_WAKE */	PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, PLTRST, YES),
-/* TBT_CIO_PLUG_EVT */	PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PU, PLTRST, YES),
-/* PCH_SLOT1_WAKE_N */	PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, PLTRST, YES),
+/* GPP_B_14_SPKR */	PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
+/* WLAN_PCIE_WAKE */	PAD_CFG_GPI_SCI(GPP_B16, NONE, PLTRST, EDGE_SINGLE, INVERT),
+/* TBT_CIO_PLUG_EVT */	PAD_CFG_GPI_SCI(GPP_B17, UP_20K, PLTRST, EDGE_SINGLE, INVERT),
+/* PCH_SLOT1_WAKE_N */	PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, EDGE_SINGLE, INVERT),
 /* CCODEC_SPI_CS */	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
-/* CODEC_SPI_CLK */	PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1),
-/* CODEC_SPI_MISO */	PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1),
-/* CODEC_SPI_MOSI */	PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
-/* SM1ALERT# */		PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP),
+/* CODEC_SPI_CLK */	PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
+/* CODEC_SPI_MISO */	PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1),
+/* CODEC_SPI_MOSI */	PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
+/* SM1ALERT# */		PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
 /* SMB_CLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-/* SMB_DATA */		PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
-/* SMBALERT# */		PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP),
+/* SMB_DATA */		PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
+/* SMBALERT# */		PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
 /* M2_WWAN_PWREN */	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
 /* SML0DATA */		PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-/* SML0ALERT# */	PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, DEEP),
+/* SML0ALERT# */	PAD_CFG_GPI_APIC_HIGH(GPP_C5, DN_20K, DEEP),
 /* EC_IN_RW */		PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
-/* USB_CTL */		PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1),
+/* USB_CTL */		PAD_CFG_NF(GPP_C7, DN_20K, DEEP, NF1),
 /* UART0_RXD */		PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
 /* UART0_TXD */		PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 /* NFC_RST* */		PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
@@ -120,13 +120,13 @@ static const struct pad_config gpio_table[] = {
 /* ISH_UART0_RTS */	PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
 /* ISH_UART0_CTS */	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
 /* DMIC_CLK_1 */	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
-/* DMIC_DATA_1 */	PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1),
+/* DMIC_DATA_1 */	PAD_CFG_NF(GPP_D18, DN_20K, DEEP, NF1),
 /* DMIC_CLK_0 */	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
-/* DMIC_DATA_0 */	PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1),
+/* DMIC_DATA_0 */	PAD_CFG_NF(GPP_D20, DN_20K, DEEP, NF1),
 /* ITCH_SPI_D2 */	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 /* ITCH_SPI_D3 */	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
 /* I2S_MCLK */		PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
-/* SPI_TPM_IRQ */	PAD_CFG_GPI_APIC(GPP_E0, 20K_PD, DEEP),
+/* SPI_TPM_IRQ */	PAD_CFG_GPI_APIC_HIGH(GPP_E0, DN_20K, DEEP),
 /* SATAXPCIE1 */	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 /* SSD_PEDET */		PAD_CFG_GPI_GPIO_DRIVER(GPP_E2, NONE, DEEP),
 /* CPU_GP0 */		PAD_CFG_GPO(GPP_E3, 1, RSMRST),
@@ -138,15 +138,15 @@ static const struct pad_config gpio_table[] = {
 /* USB2_OC_2 */		PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 /* DDI1_HPD */		PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 /* DDI2_HPD */		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
-/* EC_SMI */		PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
-/* EC_SCI */		PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, YES),
+/* EC_SMI */		PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT),
+/* EC_SCI */		PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT),
 /* EDP_HPD */		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 /* DDPB_CTRLCLK */	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
-/* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
+/* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
 /* DDPC_CTRLCLK */	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 /* DDPC_CTRLDATA */	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
-/* PCH_CODEC_IRQ */	PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
-/* TCH_PNL_RST */	PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP),
+/* PCH_CODEC_IRQ */	PAD_CFG_GPI_APIC_HIGH(GPP_E22, NONE, DEEP),
+/* TCH_PNL_RST */	PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP),
 /* I2S2_SCLK */		PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
 /* I2S2_SFRM */		PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
 /* I2S2_TXD */		PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
@@ -170,7 +170,7 @@ static const struct pad_config gpio_table[] = {
 /* EMMC_DATA7 */	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
 /* EMMC_RCLK */		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 /* EMMC_CLK */		PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
-/* WWAN_UIM_SIM_DET */	PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP),
+/* WWAN_UIM_SIM_DET */	PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP),
 /* SD_CMD */		PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
 /* SD_DATA0 */		PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
 /* SD_DATA1 */		PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
@@ -182,7 +182,7 @@ static const struct pad_config gpio_table[] = {
 /* PCH_BATLOW */	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 /* EC_PCH_ACPRESENT */	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 /* EC_PCH_WAKE */	PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
-/* EC_PCH_PWRBTN */	PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
+/* EC_PCH_PWRBTN */	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
 /* PM_SLP_S3# */	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 /* PM_SLP_S4# */	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 /* PM_SLP_SA# */	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h
index b2d72c6c9c50..37193cfcda40 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h
@@ -44,28 +44,28 @@
 /* Pad configuration in ramstage. */
 static const struct pad_config gpio_table[] = {
 /* EC_PCH_RCIN */       PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3),
-/* EC_LPC_IO0 */        PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF3),
-/* EC_LPC_IO1*/         PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF3),
-/* EC_LPC_IO2 */        PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF3),
-/* EC_LPC_IO3 */        PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF3),
+/* EC_LPC_IO0 */        PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF3),
+/* EC_LPC_IO1*/         PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF3),
+/* EC_LPC_IO2 */        PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF3),
+/* EC_LPC_IO3 */        PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF3),
 /* LPC_FRAME */         PAD_CFG_NF(GPP_A5, NONE, DEEP, NF3),
 /* LPC_SERIRQ */        PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3),
 /* PIRQAB */            PAD_CFG_GPI(GPP_A7, NONE, DEEP),
 /* LPC_CLKRUN */        PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 /* EC_LPC_CLK */        PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
-/* PCH_LPC_CLK */       PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
+/* PCH_LPC_CLK */       PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
 /* PMEB */              PAD_CFG_GPI(GPP_A11, NONE, DEEP),
 /* SUS_PWR_ACK_R */     PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
 /* PM_SUS_ESPI_RST */   PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3),
-/* PCH_SUSACK */        PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1),
+/* PCH_SUSACK */        PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
 /* BT_RF_KILL */        PAD_CFG_GPO(GPP_B3, 1, DEEP),
 /* EXTTS_SNI_DRV1 */    PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1),
-/* SRCCLKREQ0# */       PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES),
+/* SRCCLKREQ0# */       PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* PM_SLP_S0 */         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 /* PCH_PLT_RST */       PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* GPP_B_14_SPKR */     PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1),
+/* GPP_B_14_SPKR */     PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1),
 /* GSPI0_MISO */        PAD_CFG_GPO(GPP_B17, 1, DEEP),
-/* PCHHOTB */           PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2),
+/* PCHHOTB */           PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2),
 /* SMB_CLK */           PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 /* SMB_DATA */          PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 /* SMBALERT# */         PAD_CFG_GPO(GPP_C2, 1, DEEP),
@@ -85,8 +85,8 @@ static const struct pad_config gpio_table[] = {
 /* SSP0_TXD */          PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
 /* SSP0_RXD */          PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 /* SSP0_SCLK */         PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
-/* SATAE_IFDET */       PAD_CFG_NF(GPP_E0, 20K_PU, DEEP, NF1),
-/* SATAE_IFDET */       PAD_CFG_NF(GPP_E1, 20K_PU, DEEP, NF1),
+/* SATAE_IFDET */       PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),
+/* SATAE_IFDET */       PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
 /* CPU_GP0 */           PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),
 /* SSD_SATA_DEVSLP */   PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
 /* SATALED# */          PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
@@ -94,14 +94,14 @@ static const struct pad_config gpio_table[] = {
 /* USB2_OC_1 */         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
 /* USB2_OC_2 */         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 /* USB2_OC_3 */         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
-/* SATAXPCIE_4 */       PAD_CFG_NF(GPP_F1, 20K_PU, DEEP,NF1),
-/* SATA_DEVSLP_3 */     PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, YES),
+/* SATAXPCIE_4 */       PAD_CFG_NF(GPP_F1, UP_20K, DEEP,NF1),
+/* SATA_DEVSLP_3 */     PAD_CFG_GPI_SCI(GPP_F5, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* SATA_DEVSLP_4 */     PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
-/* SATA_SCLOCK */       PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP),
+/* SATA_SCLOCK */       PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, DEEP),
 /* SATA_SLOAD */        PAD_CFG_GPI(GPP_F11, NONE, DEEP),
-/* SATA_SDATAOUT1 */    PAD_CFG_GPI_APIC(GPP_F12, NONE, DEEP),
-/* SATA_SDATAOUT0 */    PAD_CFG_GPI_APIC(GPP_F13, NONE, DEEP),
-/* H_SKTOCC_N */        PAD_CFG_GPI_APIC(GPP_F14, NONE, DEEP),
+/* SATA_SDATAOUT1 */    PAD_CFG_GPI_APIC_HIGH(GPP_F12, NONE, DEEP),
+/* SATA_SDATAOUT0 */    PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, DEEP),
+/* H_SKTOCC_N */        PAD_CFG_GPI_APIC_HIGH(GPP_F14, NONE, DEEP),
 /* USB_OC4_R_N */       PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
 /* USB_OC5_R_N */       PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
 /* USB_OC6_R_N */       PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
@@ -110,44 +110,44 @@ static const struct pad_config gpio_table[] = {
 /* VCORE_VBOOST_CTRL */ PAD_CFG_GPO(GPP_F23, 0, DEEP),
 /* FAN_TACH_0 */        PAD_CFG_GPO(GPP_G0, 1, DEEP),
 /* FAN_TACH_1 */        PAD_CFG_GPO(GPP_G1, 1, DEEP),
-/* FAN_TACH_2 */        PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES),
-/* FAN_TACH_3 */        PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES),
+/* FAN_TACH_2 */        PAD_CFG_GPI_SCI(GPP_G2, NONE, DEEP, EDGE_SINGLE, INVERT),
+/* FAN_TACH_3 */        PAD_CFG_GPI_SCI(GPP_G3, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* FAN_TACH_4 */        PAD_CFG_GPO(GPP_G4, 1, DEEP),
-/* FAN_TACH_5 */        PAD_CFG_GPI_APIC(GPP_G5, NONE, DEEP),
-/* FAN_TACH_6 */        PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, DEEP, YES),
+/* FAN_TACH_5 */        PAD_CFG_GPI_APIC_HIGH(GPP_G5, NONE, DEEP),
+/* FAN_TACH_6 */        PAD_CFG_GPI_SCI(GPP_G6, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* FAN_TACH_7 */        PAD_CFG_GPO(GPP_G7, 1, DEEP),
-/* GSXDOUT */           PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES),
+/* GSXDOUT */           PAD_CFG_GPI_SCI(GPP_G12, DN_20K, DEEP, EDGE_SINGLE, INVERT),
 /* GSXSLOAD */          PAD_CFG_GPO(GPP_G13, 1, DEEP),
-/* GSXDIN */            PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, DEEP, YES),
+/* GSXDIN */            PAD_CFG_GPI_SCI(GPP_G14, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* GSXSRESETB */        PAD_CFG_GPO(GPP_G15, 0, DEEP),
 /* GSXCLK */            PAD_CFG_GPO(GPP_G16, 0, DEEP),
-/* NMIB */              PAD_CFG_GPI_APIC(GPP_G18, NONE, DEEP),
+/* NMIB */              PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, DEEP),
 /* SMIB */              PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1),
-/* TEST_SETUP_MENU */   PAD_CFG_GPI_APIC(GPP_G20, NONE, DEEP),
-/* P_INTF_N */          PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES),
+/* TEST_SETUP_MENU */   PAD_CFG_GPI_APIC_HIGH(GPP_G20, NONE, DEEP),
+/* P_INTF_N */          PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* PCH_PEGSLOT1 */      PAD_CFG_GPO(GPP_G22, 1, DEEP),
 /* IVCAM_DFU_R */       PAD_CFG_GPO(GPP_G23, 1, DEEP),
 /* SRCCLKREQB_8 */      PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
 /* SML2CLK */           PAD_CFG_GPI(GPP_H10, NONE, DEEP),
 /* SML2DATA */          PAD_CFG_GPI(GPP_H11, NONE, DEEP),
-/* SML3CLK */           PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP),
-/* SML3DATA */          PAD_CFG_GPI_APIC(GPP_H14, NONE, DEEP),
-/* SML3ALERTB */        PAD_CFG_GPI_APIC(GPP_H15, NONE, DEEP),
+/* SML3CLK */           PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, DEEP),
+/* SML3DATA */          PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, DEEP),
+/* SML3ALERTB */        PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, DEEP),
 /* SML4DATA */          PAD_CFG_GPO(GPP_H17, 1, DEEP),
 /* LED_DRIVE */         PAD_CFG_GPO(GPP_H23, 0, DEEP),
 /* DDSP_HPD_0 */        PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
 /* DDSP_HPD_1 */        PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
 /* DDSP_HPD_2 */        PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
-/* DDSP_HPD_1 */        PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES),
+/* DDSP_HPD_1 */        PAD_CFG_GPI_SMI(GPP_I3, NONE, DEEP, EDGE_SINGLE, INVERT),
 /* DDPB_CTRLCLK */      PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
-/* DDPB_CTRLDATA */     PAD_CFG_NF(GPP_I6, 20K_PD, DEEP, NF1),
+/* DDPB_CTRLDATA */     PAD_CFG_NF(GPP_I6, DN_20K, DEEP, NF1),
 /* DDPC_CTRLCLK */      PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
-/* DDPC_CTRLDATA */     PAD_CFG_NF(GPP_I8, 20K_PD, DEEP, NF1),
+/* DDPC_CTRLDATA */     PAD_CFG_NF(GPP_I8, DN_20K, DEEP, NF1),
 /* DDPD_CTRLCLK */      PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
-/* DDPD_CTRLDATA */     PAD_CFG_NF(GPP_I10, 20K_PD, DEEP, NF1),
+/* DDPD_CTRLDATA */     PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1),
 /* EC_PCH_ACPRESENT */  PAD_CFG_GPO(GPD1, 0, DEEP),
 /* EC_PCH_WAKE */       PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
-/* PM_PWRBTN_R_N */     PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
+/* PM_PWRBTN_R_N */     PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
 /* PM_SLP_S3# */        PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 /* PM_SLP_S4# */        PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 /* PM_SLP_SA# */        PAD_CFG_NF(GPD6, NONE, DEEP, NF1),