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| author | Teo Boon Tiong <boon.tiong.teo@intel.com> | 2017-09-07 00:48:55 +0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-12-19 15:36:48 +0000 |
| commit | 4dee7b528d3d85ffcca9b7f1fe02959e4113e106 (patch) | |
| tree | aa749395e82efd059383c3b5f27359afa297c72e /src/mainboard/intel/saddlebrook/Kconfig | |
| parent | 08bea22c246fe4ad181a8992f86100e9249404ae (diff) | |
| download | coreboot-4dee7b528d3d85ffcca9b7f1fe02959e4113e106.tar.gz coreboot-4dee7b528d3d85ffcca9b7f1fe02959e4113e106.tar.bz2 coreboot-4dee7b528d3d85ffcca9b7f1fe02959e4113e106.zip | |
mainboard/intel/saddlebrook: add support for Saddle Brook
Add initial files to support the Saddle Brook board. This board uses the
Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file.
Most of the code has been taken carried over from kunimitsu with changes
done for Saddle Brook.
Saddle Brook is a reference board for Skylake SOC and has DDR4.
TEST=Build with uefi payload and boot to Linux 4.9 on CRB successfully.
Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e
Signed-off-by: Anuj Mittal <anujx.mittal@intel.com>
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/21436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/intel/saddlebrook/Kconfig')
| -rw-r--r-- | src/mainboard/intel/saddlebrook/Kconfig | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig new file mode 100644 index 000000000000..df0428617e57 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_INTEL_SKLSDLBRK + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CONSOLE_SERIAL + select DRIVERS_UART + select GENERIC_SPD_BIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select SERIRQ_CONTINUOUS_MODE + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_SKYLAKE + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select SADDLEBROOK_USES_FSP1_1 + select HAVE_CMOS_DEFAULT + + +config SADDLEBROOK_USES_FSP1_1 + bool "FSP driver 1.1" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "intel/saddlebrook" + +config MAINBOARD_PART_NUMBER + string + default "Skylake Saddle Brook" + +config MAINBOARD_FAMILY + string + default "Intel_SaddleBrook" + +config MAX_CPUS + int + default 8 + +config TPM_PIRQ + hex + default 0x18 # GPP_E0_IRQ + +endif |