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| author | Felix Singer <felixsinger@posteo.net> | 2020-07-25 14:01:52 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-07-29 20:58:58 +0000 |
| commit | 91dfb920383a8761711e1312f2bcffd2f9529dfb (patch) | |
| tree | c59d0834ada7b19e8dc6699c92697894447b4388 /src/mainboard/intel/saddlebrook | |
| parent | aff69be254096a3a9d630551780c5610b7db15fa (diff) | |
| download | coreboot-91dfb920383a8761711e1312f2bcffd2f9529dfb.tar.gz coreboot-91dfb920383a8761711e1312f2bcffd2f9529dfb.tar.bz2 coreboot-91dfb920383a8761711e1312f2bcffd2f9529dfb.zip | |
soc/intel/skylake: Enable HECI3 depending on devicetree configuration
Currently HECI3 gets enabled by the option Heci3Enabled, but
this duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the HECI3 controller.
I checked all corresponding mainboards if the devicetree configuration
matches the Heci3Enabled setting.
Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/saddlebrook')
| -rw-r--r-- | src/mainboard/intel/saddlebrook/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 944cb50c33aa..a8066d5cb2bf 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -25,7 +25,6 @@ chip soc/intel/skylake register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "0" - register "Heci3Enabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" |