diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2021-04-08 15:47:24 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-21 09:11:07 +0000 |
| commit | 72e736d8e82103a7a97d28ea4aaf8c2cb927a112 (patch) | |
| tree | 861bb6856a20449fee2f0dc8e3167fd97d679ebc /src/mainboard/intel/shadowmountain | |
| parent | 5a19f7e3ceaa44a0c3cb1a78f28801b792c7c7a6 (diff) | |
| download | coreboot-72e736d8e82103a7a97d28ea4aaf8c2cb927a112.tar.gz coreboot-72e736d8e82103a7a97d28ea4aaf8c2cb927a112.tar.bz2 coreboot-72e736d8e82103a7a97d28ea4aaf8c2cb927a112.zip | |
mb/intel/shadowmountain: Disable GSPI1 interface connected to FPS
The patch disables GSPI1 interface connected to fingerprint scanner since
no plans to enable FPS on Shadowmountain.
TEST=Verified on Shadowmountain
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic693a8c9699d7d1cceef9ca26305cc34498022d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/mainboard/intel/shadowmountain')
| -rw-r--r-- | src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c | 8 |
2 files changed, 2 insertions, 10 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 5b3dbbf583db..ac7c31d3cf1d 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -91,19 +91,17 @@ chip soc/intel/alderlake register "SerialIoGSpiMode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ [PchSerialIoIndexGSPI0] = 1, - [PchSerialIoIndexGSPI1] = 1, }" register "SerialIoGSpiCsState" = "{ [PchSerialIoIndexGSPI0] = 1, - [PchSerialIoIndexGSPI1] = 1, }" register "SerialIoUartMode" = "{ diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c index 090715e25c71..8d7778c9c191 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c @@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = { /* A18 : HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* A21 : EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* A22 : EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP), /* A23 : EN_SPKR_PA */ @@ -204,12 +204,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, EDGE_BOTH), /* F10 : EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO(GPP_F10, 0, DEEP), - /* F11 : PCH_GSPI1_FPMCU_CLK */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), - /* F12 : PCH_GSPI1_FPMCU_MISO */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), - /* F13 : PCH_GSPI1_FPMCU_MISO */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), /* F14 : WLAN_RST_ODL */ PAD_CFG_GPO(GPP_F14, 1, DEEP), /* F15 : RCAM_RST_L */ |