mb/intel/tglrvp: Add initial mainboard code

This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.

This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761

Below are the changes done over the copy patch:

 1. Rename "Icelake" with "Tigerlake".
 2. Replace "icelake_rvp" with "tglrvp".
 3. Rename "icl" with "tgl".
 4. Remove unwanted SPD file, add empty SPD as
    placeholder.
 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake".
 6. Empty romstage_fsp_params.c, to fill it later with
    SOC specific config.
 7. Empty GPIO configuration, to be filled as per board.
 8. Change copyright year to 2019.
 9. Add board support namely BOARD_INTEL_TGLRVP_UP3
 10. Replace icl_u and icl_y variant with tglrvp variant.
 11. Remove basebord gpio.c and rely on variant override.
 12. Remove HDA verb table and config support.

Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs.
 2. Clean up devicetree as per tigerlake SOC.
 3. Add GPIO support.
 4. Update chromeos.fmd to make 32MB BIOS region.
 5. clean up and make empty devicetree setting

TEST=Build tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>

1 files changed, 54 insertions, 0 deletions

diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig
new file mode 100644
index 000000000000..bee72cfdbea8
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/Kconfig
@@ -0,0 +1,54 @@
+if BOARD_INTEL_TGLRVP_UP3
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_32768
+	select EC_ACPI
+	select GENERIC_SPD_BIN
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_CHROMEOS
+	select GENERIC_SPD_BIN
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_USB_ACPI
+	select SOC_INTEL_TIGERLAKE
+	select MAINBOARD_USES_IFD_EC_REGION
+	select INTEL_LPSS_UART_FOR_CONSOLE
+
+config MAINBOARD_DIR
+	string
+	default "intel/tglrvp"
+
+config VARIANT_DIR
+	string
+	default "tglrvp_up3" if BOARD_INTEL_TGLRVP_UP3
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "tglrvp"
+
+config MAINBOARD_FAMILY
+	string
+	default "Intel_tglrvp"
+
+config MAX_CPUS
+	int
+	default 8
+
+config DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config VBOOT
+	select VBOOT_LID_SWITCH
+	select VBOOT_MOCK_SECDATA
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+endif