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| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-07-05 17:15:51 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-08 15:48:47 +0000 |
| commit | 681a59d5c38a2ea4d800f35510f45756f4d687ac (patch) | |
| tree | 1c7faf845fc3be3fa0a5e9b76f2a395359036b1f /src/mainboard/intel/tglrvp/variants | |
| parent | 270e25594faab04c4db402b47922af8740673777 (diff) | |
| download | coreboot-681a59d5c38a2ea4d800f35510f45756f4d687ac.tar.gz coreboot-681a59d5c38a2ea4d800f35510f45756f4d687ac.tar.bz2 coreboot-681a59d5c38a2ea4d800f35510f45756f4d687ac.zip | |
mb/intel/tglrvp: Update Power Limit2 minimum value
Update Power Limit2 (PL2) minimum value to the same as maximum value.
DTT does not throttle PL2, so this minimum value change here does not
impact any existing behavior on the system.
BUG=None
BRANCH=None
TEST=Build and test on tglrvp system
Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index ce7c3d96a56c..4e3d2e798ead 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -191,7 +191,7 @@ chip soc/intel/tigerlake .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 15000, + .min_power = 60000, .max_power = 60000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 47ac01e57159..7f7e16b10a30 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -195,7 +195,7 @@ chip soc/intel/tigerlake .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 9000, + .min_power = 40000, .max_power = 40000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, |