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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-16 14:02:25 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-18 19:03:22 +0000 |
| commit | 157b189f6b97b6e9ecd8d29edbbd045fbbc231f5 (patch) | |
| tree | 4562bd212e40d0832fa893935d85a06d82f8a897 /src/mainboard/intel | |
| parent | 146c09823333c52e8bbca98465ccc8512ec1daa2 (diff) | |
| download | coreboot-157b189f6b97b6e9ecd8d29edbbd045fbbc231f5.tar.gz coreboot-157b189f6b97b6e9ecd8d29edbbd045fbbc231f5.tar.bz2 coreboot-157b189f6b97b6e9ecd8d29edbbd045fbbc231f5.zip | |
cpu/intel: Enter romstage without BIST
When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/baskingridge/romstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/d945gclf/romstage.c | 9 | ||||
| -rw-r--r-- | src/mainboard/intel/dg41wv/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/dg43gt/romstage.c | 4 |
4 files changed, 5 insertions, 15 deletions
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index b43110bab10f..3fd9aab9c722 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -63,7 +63,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -136,7 +136,6 @@ void mainboard_romstage_entry(unsigned long bist) .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = NULL, }; diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 32b9a9febac3..15acffb05295 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -19,7 +19,6 @@ #include <cpu/x86/lapic.h> #include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -117,12 +116,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); /* Enable SuperIO PM */ @@ -132,9 +130,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 2d6e916d5a3f..ec3e2bfbe6f1 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> @@ -75,7 +74,7 @@ static void ich7_enable_lpc(void) pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -89,7 +88,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index c7ef09d8db95..db896824cdd8 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -20,7 +20,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/common/winbond.h> @@ -68,7 +67,7 @@ static void ich10_enable_lpc(void) pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; u8 boot_path = 0; @@ -81,7 +80,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); |