diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-11-02 10:36:20 +0200 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-06 17:40:50 +0000 |
commit | 4fdd84e716bb052bfbae58366c687be2656a97bb (patch) | |
tree | 1bdd3c1bed7b16f61ce971a0a552400257e58f88 /src/mainboard/intel | |
parent | afe5562ca39b26cc42ca04da55b68f73a7b70654 (diff) | |
download | coreboot-4fdd84e716bb052bfbae58366c687be2656a97bb.tar.gz coreboot-4fdd84e716bb052bfbae58366c687be2656a97bb.tar.bz2 coreboot-4fdd84e716bb052bfbae58366c687be2656a97bb.zip |
ChromeOS: Promote variant_cros_gpio()
The only purpose of mainboard_chromeos_acpi_generate()
was to pass cros_gpio array for ACPI \\OIPG package
generation.
Promote variant_cros_gpio() from baseboards to ChromeOS
declaration.
Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
22 files changed, 21 insertions, 108 deletions
diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index d7e55a91dc67..56fbc5057dab 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -42,15 +40,6 @@ int get_write_protect_state(void) return 0; } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - #if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) ||\ CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)) int get_ec_is_trusted(void) diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 62ae0f38c0d2..33b5a1dc3745 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -2,6 +2,8 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/intel/adlrvp/gpio_n.c b/src/mainboard/intel/adlrvp/gpio_n.c index 6f4e4a5987c9..364deaca2576 100644 --- a/src/mainboard/intel/adlrvp/gpio_n.c +++ b/src/mainboard/intel/adlrvp/gpio_n.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 143679ac5678..4ae10112cea5 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> enum adl_boardid { /* ADL-P LPDDR4 RVPs */ @@ -28,9 +27,6 @@ enum adl_boardid { ADL_N_LP5 = 0x7, }; -/* The next set of functions return the gpio table and fill in the number of - * entries for each table. */ -const struct cros_gpio *variant_cros_gpios(size_t *num); /* Functions to configure GPIO as per variant schematics */ void variant_configure_gpio_pads(void); void variant_configure_early_gpio_pads(void); diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index d4408f4d0604..05280b15879f 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -47,7 +47,8 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 5c5003b7a90e..b2ea87f22c5e 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -1,13 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -35,12 +33,3 @@ int get_write_protect_state(void) /* No write protect */ return 0; } - -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h index b7a1616e4638..6ae25d4d8487 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,6 @@ #include <soc/cnl_memcfg_init.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ @@ -13,8 +12,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); - /* Return memory configuration structure. */ const struct cnl_mb_cfg *variant_memcfg_config(void); diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 2d0e2e1f44ec..621ecfdf75ec 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -44,7 +44,8 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 7a14c86bd269..bc27b27f3195 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <variant/gpio.h> @@ -26,15 +24,6 @@ int get_write_protect_state(void) return 0; } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int __weak get_lid_switch(void) { return -1; diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h index f1df93783d8d..24c28f9ccd5c 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> -#include <vendorcode/google/chromeos/chromeos.h> /** * variant_board_id() - Get the board id for the current board variant @@ -27,9 +26,6 @@ const struct lpddr4_cfg *variant_lpddr4_config(void); /* Return memory SKU for the board. */ size_t variant_memory_sku(void); -/* Return ChromeOS gpio table and fill in number of entries. */ -const struct cros_gpio *variant_cros_gpios(size_t *num); - /* Seed the NHLT tables with the board specific information. */ struct nhlt; void variant_nhlt_init(struct nhlt *nhlt); diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 6df26afced9e..2b1f9aff3a20 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -2,12 +2,10 @@ #include <acpi/acpi.h> #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -35,12 +33,3 @@ int get_write_protect_state(void) /* No write protect */ return 0; } - -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h index ccbadca56c31..48d6c1c738f9 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -4,13 +4,11 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index bf9a7bf8b91f..ef0d7ec2abcc 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -37,12 +35,3 @@ int get_write_protect_state(void) /* No write protect */ return 0; } - -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h index e2e331a29538..120833fecf3a 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> enum jsl_board_id { jsl_ddr4 = 1, @@ -18,7 +17,6 @@ enum jsl_board_id { const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); const struct mb_cfg *variant_memcfg_config(uint8_t board_id); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index afc27cd6d5df..f64f5bd96c3b 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -60,9 +60,10 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 87a0e01b4185..2bb59fb6941f 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -31,9 +31,10 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c index 085875443690..1e7c7d94942c 100644 --- a/src/mainboard/intel/shadowmountain/chromeos.c +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -26,15 +24,6 @@ int get_write_protect_state(void) return gpio_get(GPIO_PCH_WP); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int get_ec_is_trusted(void) { /* EC is trusted if not in RW. */ diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h index a145ac98593f..e8886d924fd0 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> #include <stddef.h> -#include <vendorcode/google/chromeos/chromeos.h> /* * The next set of functions return the gpio table and fill in the number of @@ -14,7 +13,6 @@ */ const struct pad_config *variant_base_gpio_table(size_t *num); const struct pad_config *variant_override_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); void variant_configure_early_gpio_pads(void); diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 91ce9aed2759..a6a0af24ae63 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -38,7 +38,8 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index dd6c6667941a..779c9a0f4735 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -39,15 +37,6 @@ int get_write_protect_state(void) return 0; } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int get_ec_is_trusted(void) { /* Do not have a Chrome EC involved in entering recovery mode; diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index fbb86f7b002f..45ae15e4d671 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -5,14 +5,12 @@ #include <soc/gpio.h> #include <soc/meminit.h> -#include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); size_t variant_memory_sku(void); const struct mb_cfg *variant_memory_params(void); diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 5e01910e4836..49da437ed3a2 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -36,7 +36,8 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } |