diff options
| author | Anil Kumar <anil.kumar.k@intel.com> | 2023-10-24 14:22:51 -0700 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-11-01 15:34:11 +0000 |
| commit | a8962492b224c84a48c041a414ccbc3b6e8e4869 (patch) | |
| tree | 213dfe7be732ae285c5ed3d860d4f3ca432cd51a /src/mainboard/intel | |
| parent | da48d9ebfe30d65348bd337bda1f502c91a71970 (diff) | |
| download | coreboot-a8962492b224c84a48c041a414ccbc3b6e8e4869.tar.gz coreboot-a8962492b224c84a48c041a414ccbc3b6e8e4869.tar.bz2 coreboot-a8962492b224c84a48c041a414ccbc3b6e8e4869.zip | |
mb/{google,intel}: Update FMD to support CBFS verification
This patch adds the required FMD changes to support the change
in cse_lite 'commit Ie0266e50463926b8d377825 ("remove
cbfs_unverified_area_map() API in cse_lite")' for CBFS verification.
With the change in cse_lite the ME_RW_A/B blobs are now part of
FW_MAIN_A/B and corresponding entries in FMD can be removed for boards
that currently use them.
BUG=b:284382452
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/chromeos.fmd | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/chromeos.fmd | 10 | ||||
| -rw-r--r-- | src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/mtlrvp/chromeos.fmd | 2 |
4 files changed, 4 insertions, 12 deletions
diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index 53469de9c2ac..0e8d321f8561 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -15,7 +15,6 @@ FLASH 32M { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3520K } RW_LEGACY(CBFS) 1M RW_MISC 1M { @@ -39,7 +38,6 @@ FLASH 32M { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3520K } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index e4e0b242e0dc..4fe11debf215 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -8,15 +8,13 @@ FLASH@0xff000000 0x1000000 { RW_LEGACY(CBFS)@0x0 0x100000 RW_SECTION_A@0x100000 0x3a4800 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x2127c0 - RW_FWID_A@0x2147c0 0x40 - ME_RW_A(CBFS)@0x214800 0x190000 + FW_MAIN_A(CBFS)@0x2000 0x3a27c0 + RW_FWID_A@0x3a47c0 0x40 } RW_SECTION_B@0x4a4800 0x3a4800 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x2127c0 - RW_FWID_B@0x2147c0 0x40 - ME_RW_B(CBFS)@0x214800 0x190000 + FW_MAIN_B(CBFS)@0x2000 0x3a27c0 + RW_FWID_B@0x3a47c0 0x40 } RW_MISC@0x849000 0x36000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { diff --git a/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd index 6ca1cc68c0a0..d0856406a37b 100644 --- a/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd @@ -8,7 +8,6 @@ FLASH 32M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 4400K } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, @@ -18,7 +17,6 @@ FLASH 32M { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 4400K } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd index a5bc538873a4..c32a9f0675d1 100644 --- a/src/mainboard/intel/mtlrvp/chromeos.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos.fmd @@ -8,7 +8,6 @@ FLASH 32M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 4400K } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, @@ -18,7 +17,6 @@ FLASH 32M { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 4400K } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { |