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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-04-28 18:32:35 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-03 07:42:51 +0000 |
| commit | e46e740f9155a7beeb11358b2312c3a6f6922979 (patch) | |
| tree | 63558bd91502aed2079dc057f7f69588ee56cb93 /src/mainboard/intel | |
| parent | 60d67ce924c48832b14487e396e6684fb9243827 (diff) | |
| download | coreboot-e46e740f9155a7beeb11358b2312c3a6f6922979.tar.gz coreboot-e46e740f9155a7beeb11358b2312c3a6f6922979.tar.bz2 coreboot-e46e740f9155a7beeb11358b2312c3a6f6922979.zip | |
mb/intel/adlrvp: Increase RO/RW region size in chromeos.fmd
While building adlrvp board with chromeos.fmd and adding all chromeos
related artifacts, RO region is running out of space. Also, we need
to increase RW region size to accommodate all binaries and artifacts.
Aligning chromeos.fmd with Brya will help in solving this issue, thus
aligning chromeos.fmd with Brya.
BUG=b:184997582
BRANCH=NONE
TEST=Code compiles fine and able to boot adlrvp platform
Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52732
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/chromeos.fmd | 70 |
1 files changed, 38 insertions, 32 deletions
diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index e8755ba49e5f..5c9ef4744038 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -1,42 +1,48 @@ -FLASH@0xfe000000 32M { - SI_ALL@0x0 0x1000000 { - SI_DESC 0x1000 - SI_EC 0x80000 +FLASH 32M { + SI_ALL 6M { + SI_DESC 4K + SI_EC 512K SI_ME } - SI_BIOS@0x1400000 0xc00000 { - RW_SECTION_A 0x368000 { - VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x357fc0 - RW_FWID_A 0x40 + SI_BIOS 26M { + RW_SECTION_A 8M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 3M } - RW_SECTION_B 0x368000 { - VBLOCK_B 0x10000 - FW_MAIN_B(CBFS) 0x357fc0 - RW_FWID_B 0x40 - } - RW_MISC 0x30000 { - UNIFIED_MRC_CACHE(PRESERVE) 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 + RW_LEGACY(CBFS) 1M + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 192K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 128K } - RW_ELOG(PRESERVE) 0x4000 - RW_SHARED 0x4000 { - SHARED_DATA 0x2000 - VBLOCK_DEV 0x2000 + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K } - RW_VPD(PRESERVE) 0x2000 - RW_NVRAM(PRESERVE) 0x6000 + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # This section starts at the 16M boundary in SPI flash. + # ADL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 3M } - # RW_LEGACY needs to be minimum of 1MB - RW_LEGACY(CBFS) 0x100000 - WP_RO { - RO_VPD(PRESERVE) 0x4000 + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 8M { + RO_VPD(PRESERVE) 16K RO_SECTION { - FMAP 0x800 - RO_FRID 0x40 - RO_FRID_PAD 0x7c0 - GBB 0x3000 + FMAP 2K + RO_FRID 64 + GBB@4K 448K COREBOOT(CBFS) } } |