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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-01 23:22:55 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 13:57:06 +0000 |
| commit | f9decbb0c720662d8e71fe221aef55b7ecf76196 (patch) | |
| tree | 06b2198767b4c86b7d36e7ddd6a5f56b4a1fbc54 /src/mainboard/jetway/nf81-t56n-lf/dsdt.asl | |
| parent | e56f0c7cab77b89a750b4a3f7f380b1a10cd0d1d (diff) | |
| download | coreboot-f9decbb0c720662d8e71fe221aef55b7ecf76196.tar.gz coreboot-f9decbb0c720662d8e71fe221aef55b7ecf76196.tar.bz2 coreboot-f9decbb0c720662d8e71fe221aef55b7ecf76196.zip | |
mb/*/*: Remove AMD family14 boards
These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I3495d140a244bbbf63e846fcd963d69907e09719
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/jetway/nf81-t56n-lf/dsdt.asl')
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/dsdt.asl | 46 |
1 files changed, 0 insertions, 46 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl deleted file mode 100644 index 5feb9f277e24..000000000000 --- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* DefinitionBlock Statement */ -#include <acpi/acpi.h> -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - #include <acpi/dsdt_top.asl> - - #include <cpu/amd/agesa/family14/acpi/cpu.asl> - - #include "acpi/routing.asl" - - Scope(\_SB) { - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - Device(PCI0) { - - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/cimx/sb800/acpi/fch.asl> - - } - } /* End Scope(_SB) */ - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - #include "acpi/gpe.asl" - #include "acpi/usb_oc.asl" - - #include "acpi/superio.asl" -} -/* End of ASL file */ |