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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-30 04:14:19 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-10-05 13:21:00 +0000 |
| commit | ad787e18e0ed24495132d0e9e638ed835afad354 (patch) | |
| tree | 9ee07a78a871830740879127c7c3f14094a57dd1 /src/mainboard/kontron/986lcd-m/romstage.c | |
| parent | 81ade745b19194fbad3e3d51d0dac6ca76de1f01 (diff) | |
| download | coreboot-ad787e18e0ed24495132d0e9e638ed835afad354.tar.gz coreboot-ad787e18e0ed24495132d0e9e638ed835afad354.tar.bz2 coreboot-ad787e18e0ed24495132d0e9e638ed835afad354.zip | |
intel/i945,i82801gx: Refactor early PCI bridge reset
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/kontron/986lcd-m/romstage.c')
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/romstage.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index cee7c2a603ed..c0e60713011a 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -15,7 +15,6 @@ #include <stdint.h> #include <cf9_reset.h> -#include <delay.h> #include <console/console.h> #include <arch/romstage.h> #include <cpu/x86/lapic.h> @@ -246,10 +245,8 @@ void mainboard_romstage_entry(void) enable_lapic(); - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); + /* Force PCIRST# to conventional PCI slot and Firewire. */ + ich7_p2p_secondary_reset(); ich7_enable_lpc(); early_superio_config_w83627thg(); |