mb/lenvovo/*: Clean mainboard.c and devicetree

* Move board specific SPI registers to devicetree
* Remove unused headers
* Remove obsolete methods
* Fix coding style
* Fix Thinkpad L520 SPI lvscc register

Except for Thinkpad L520, no functional change has been done,
just moving stuff around.

Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

2 files changed, 37 insertions, 40 deletions

diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb
index 221168028ae6..542b06a9cd54 100644
--- a/src/mainboard/lenovo/l520/devicetree.cb
+++ b/src/mainboard/lenovo/l520/devicetree.cb
@@ -15,8 +15,8 @@ chip northbridge/intel/sandybridge
 	register "gpu_panel_power_up_delay" = "0"
 	register "gpu_pch_backlight" = "0x00000000"
 
-        # Override fuse bits that hard-code the value to 666 Mhz
-        register "max_mem_clock_mhz" = "933"
+	# Override fuse bits that hard-code the value to 666 Mhz
+	register "max_mem_clock_mhz" = "933"
 
 	device cpu_cluster 0x0 on
 		chip cpu/intel/socket_rPGA989
@@ -36,14 +36,14 @@ chip northbridge/intel/sandybridge
 	end
 
 	device domain 0x0 on
-                device pci 00.0 on # Host bridge Host bridge
-                        subsystemid 0x17aa 0x21dd
-                end
-                device pci 01.0 on # PCIe Bridge for discrete graphics
-                end
-                device pci 02.0 on # Internal graphics VGA controller
-                        subsystemid 0x17aa 0x21dd
-                end
+		device pci 00.0 on # Host bridge Host bridge
+			subsystemid 0x17aa 0x21dd
+		end
+		device pci 01.0 on # PCIe Bridge for discrete graphics
+		end
+		device pci 02.0 on # Internal graphics VGA controller
+			subsystemid 0x17aa 0x21dd
+		end
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
 			register "c2_latency" = "0x0065"
 			register "docking_supported" = "1"
@@ -58,6 +58,10 @@ chip northbridge/intel/sandybridge
 			register "pcie_port_coalesce" = "1"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x3b"
+
+			register "spi_uvscc" = "0"
+			register "spi_lvscc" = "0x2005"
+
 			device pci 16.0 on # Management Engine Interface 1
 				subsystemid 0x17aa 0x21dd
 			end
@@ -111,27 +115,27 @@ chip northbridge/intel/sandybridge
 					end
 				end
 				chip ec/lenovo/h8
-                                        register "config0" = "0xa7"
-                                        register "config1" = "0x09"
-                                        register "config2" = "0xa0"
-                                        register "config3" = "0xc2"
+					register "config0" = "0xa7"
+					register "config1" = "0x09"
+					register "config2" = "0xa0"
+					register "config3" = "0xc2"
 
-                                        register "beepmask0" = "0x00"
-                                        register "beepmask1" = "0x86"
-                                        register "has_power_management_beeps" = "0"
-                                        register "event2_enable" = "0xff"
-                                        register "event3_enable" = "0xff"
-                                        register "event4_enable" = "0xff"
-                                        register "event5_enable" = "0xff"
-                                        register "event6_enable" = "0xff"
-                                        register "event7_enable" = "0xff"
-                                        register "event8_enable" = "0xff"
-                                        register "event9_enable" = "0xff"
-                                        register "eventa_enable" = "0xff"
-                                        register "eventb_enable" = "0xff"
-                                        register "eventc_enable" = "0xff"
-                                        register "eventd_enable" = "0xff"
-                                        register "evente_enable" = "0xff"
+					register "beepmask0" = "0x00"
+					register "beepmask1" = "0x86"
+					register "has_power_management_beeps" = "0"
+					register "event2_enable" = "0xff"
+					register "event3_enable" = "0xff"
+					register "event4_enable" = "0xff"
+					register "event5_enable" = "0xff"
+					register "event6_enable" = "0xff"
+					register "event7_enable" = "0xff"
+					register "event8_enable" = "0xff"
+					register "event9_enable" = "0xff"
+					register "eventa_enable" = "0xff"
+					register "eventb_enable" = "0xff"
+					register "eventc_enable" = "0xff"
+					register "eventd_enable" = "0xff"
+					register "evente_enable" = "0xff"
 
 					device pnp ff.2 on # dummy
 						io 0x60 = 0x62
diff --git a/src/mainboard/lenovo/l520/mainboard.c b/src/mainboard/lenovo/l520/mainboard.c
index f7332256c4ab..526a173ec305 100644
--- a/src/mainboard/lenovo/l520/mainboard.c
+++ b/src/mainboard/lenovo/l520/mainboard.c
@@ -17,20 +17,13 @@
 
 #include <device/device.h>
 #include <drivers/intel/gma/int15.h>
-#include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/lenovo/h8/h8.h>
 
-static void mainboard_init(device_t dev)
-{
-	RCBA32(0x38c8) = 0x00000000;
-	RCBA32(0x38c4) = 0x00000000;
-}
-
 static void mainboard_enable(device_t dev)
 {
-	dev->ops->init = mainboard_init;
-
-	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+					GMA_INT15_PANEL_FIT_DEFAULT,
+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 
 void h8_mainboard_init_dock(void)