diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-10-24 17:44:20 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-26 22:38:43 +0200 |
| commit | 606b8bccb53e5bbc840d29657faaf333eff51e38 (patch) | |
| tree | e88c0abbdb799094a8362ac2fe5ccb3fe74bbcb2 /src/mainboard/lenovo/t400/devicetree.cb | |
| parent | 04be6b5949dae23ad989a35a2e6e6f750add6d04 (diff) | |
| download | coreboot-606b8bccb53e5bbc840d29657faaf333eff51e38.tar.gz coreboot-606b8bccb53e5bbc840d29657faaf333eff51e38.tar.bz2 coreboot-606b8bccb53e5bbc840d29657faaf333eff51e38.zip | |
nb/gm45/gma.c: Remove writes to DP, FDI registers
Those registers are only used on more recent Intel platforms featuring a
PCH. The DP registers on G4X hardware are at a different offset.
Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17110
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/lenovo/t400/devicetree.cb')
| -rw-r--r-- | src/mainboard/lenovo/t400/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 6bf25fab3861..9940bb7eef36 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -4,7 +4,6 @@ chip northbridge/intel/gm45 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 |